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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5121E Rev. 1, 10/2008
MPC5121E/MPC5123
MPC5121E/MPC5123 Data Sheet
The MPC5121E/MPC5123 integrates a high performance e300 CPU core based on the Power Architecture Technology with a rich set of peripheral functions focused on communications and systems integration. Major features of the MPC5121E/MPC5123 are: * e300 Power Architecture processor core (enhanced version of the MPC603e core), operates up to 400 MHz * Power modes include doze, nap, sleep, deep sleep, and hibernate * AXE - fully programmable, 200 MHz 32-bit RISC core for real-time acceleration tasks, such as audio. * MBX Lite - 2D/3D graphics engine with PowerVR vector processing (only in MPC5121E, not in MPC5123) * DIU - Display interface unit * DDR1, DDR2, and low-power mobile DDR (LPDDR) SDRAM memory controller * USB 2.0 OTG controller with integrated physical layer (PHY) * DMA subsystem * EMB - Flexible multi-function external memory bus interface * NFC - NAND flash controller * 10/100Base Ethernet * PCI interface, version 2.3 * PATA - Parallel ATA integrated development environment (IDE) controller * SATA - Serial ATA controller with integrated physical layer (PHY) * SDHC - MMC/SD/SDIO card host controller * PSC - Programmable serial controller * S/PDIF - Serial audio interface * CAN - Controller area network * BDLC - J1850 interface * VIU - Video Input, ITU-656 complient Figure 1 shows a simplified MPC5121E/MPC5123 block diagram.
TEPBGA 27 mm x 27 mm
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary
Table of Contents
1 2 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .16 3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .16 3.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . .16 3.1.2 Recommended Operating Conditions . . . . . . . .17 3.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .18 3.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .20 3.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .22 3.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .23 3.2 Oscillator and PLL Electrical Characteristics . . . . . . . .24 3.2.1 System Oscillator Electrical Characteristics . . .25 3.2.2 RTC Oscillator Electrical Characteristics . . . . . .25 3.2.3 System PLL Electrical Characteristics. . . . . . . .25 3.2.4 e300 Core PLL Electrical Characteristics . . . . .26 3.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .27 3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .27 3.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .31 3.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3.6 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.7 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.8 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.3.9 PATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.3.10 SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.3.11 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.3.12 USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3.13 On-Chip USB PHY . . . . . . . . . . . . . . . . . . . . . . 59 3.3.14 SDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.15 DIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.16 SPDIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.17 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.19 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.20 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.21 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 72 3.3.22 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.23 IEEE 1149.1 (JTAG) . . . . . . . . . . . . . . . . . . . . . 73 3.3.24 VIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 75 4.2 System and CPU Core AVDD Power Supply Filtering. 75 4.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 76 4.4 Pull-Up/Pull-Down Resistor Requirements . . . . . . . . . 77 4.4.1 Pull-Down Resistor Requirements for TEST pin 77 4.4.2 Pull-Up Requirements for the PCI Control Lines77 4.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.1 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.2 e300 COP/BDM Interface . . . . . . . . . . . . . . . . 78 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 82 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4
5
6
MPC5121E/MPC5123 Data Sheet, Rev. 1 2
Preliminary
Freescale Semiconductor
Ordering Information
Functionally Multiplexed I/O
Display
DDR1/2 Memory
83 MHz IP Bus
LPC EMB NFC PATA
AXE Engine 8 KB I-Cache
VIU DIU
Multi-Port Memory Controller
MBX Lite Graphics Engine with Vector Processing DMA 64-Channel
200 MHz AHB (32-Bit)
not available in MPC5123
FEC USB2 + PHY USB2 ULPI SATA + PHY
128 KB SRAM 200 MHz CSB Bus (64-Bit)
JTAG/COP RESET/ CLOCK
Temp
Fuse 83 MHz (max) IP Bus
e300 PowerPCTM 32-KB I-/32-KB DCache
PCI
PSC 12
SPDIF
CAN 4
SDHC
J1850
GPIO
WDT
I2 C 3
PMC
CFM
GPT
Figure 1. Simplified MPC5121E/MPC5123 Block Diagram
1
Ordering Information
Table 1. MPC5121E Orderable Part Numbers
Freescale Part Number MPC5121VY400B MPC5121VY400BR MPC5121YVY400B MPC5121YVY400BR SPC5121YVY400B SPC5121YVY400BR Speed (MHz) 400 400 400 400 400 400 Temperature (ambient) 0oC to 70oC 0oC to 70oC -40 C to 85 C -40
oC o o
Qualification Consumer Consumer Industrial Industrial
Package RoHS and Pb-free
Availability Tray
RoHS and Pb-free Tape and Reel RoHS and Pb-free Tray
to to
85oC 85oC
RoHS and Pb-free Tape and Reel Tray
-40oC
Automotive - AEC RoHS and Pb-free
-40oC to 85oC
Automotive - AEC RoHS and Pb-free Tape and Reel
Table 2. MPC5123 Orderable Part Numbers
Freescale Part Number MPC5123VY300B MPC5123VY300BR MPC5123YVY300B MPC5123YVY300BR Speed (MHz) 300 300 300 300 Temperature (ambient) 0oC to 70oC 0
oC
Qualification Consumer Consumer Industrial Industrial
Package RoHS and Pb-free
Availability Tray
to
70oC
RoHS and Pb-free Tape and Reel RoHS and Pb-free Tray
-40oC to 85oC -40 C to 85 C
o o
RoHS and Pb-free Tape and Reel
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
RTC
IPIC
3
Pin Assignments
Table 2. MPC5123 Orderable Part Numbers (continued)
Freescale Part Number SPC5123YVY300B SPC5123YVY300BR MPC5123VY400B MPC5123VY400BR MPC5123YVY400B MPC5123YVY400BR SPC5123YVY400B SPC5123YVY400BR Speed (MHz) 300 300 400 400 400 400 400 400 Temperature (ambient) -40oC to 85oC -40o
o
Qualification
Package
Availability Tray
Automotive - AEC RoHS and Pb-free
C to 85 C
o
o
Automotive - AEC RoHS and Pb-free Tape and Reel Consumer Consumer Industrial Industrial RoHS and Pb-free Tray
0 C to 70 C 0oC to 70oC -40oC to 85oC -40 C to 85 C -40o C to 85 C
o o o
RoHS and Pb-free Tape and Reel RoHS and Pb-free Tray
RoHS and Pb-free Tape and Reel Tray
Automotive - AEC RoHS and Pb-free
-40oC to 85oC
Automotive - AEC RoHS and Pb-free Tape and Reel
2
2.1
Pin Assignments
Pinout Listings
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 1 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
This section details pin assignments.
Table 3 provides the pin-out listing for the MPC5121E/MPC5123.
DDR Memory Interface (67 Total) MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 AF5 AB6 AE4 AF6 AF7 AB8 AD6 AE6 AC7 AF8 AB9 AD7 AE9 AF10 AC9 AF11 DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 4
Preliminary
Freescale Semiconductor
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 2 of 12)
Signal MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 MDQ27 MDQ28 MDQ29 MDQ30 MDQ31 MDM0 MDM1 MDM2 MDM3 MDQS0 MDQS1 MDQS2 MDQS3 MBA0 MBA1 MBA2 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 Package Pin Number AD10 AF12 AD11 AB12 AD12 AB13 AF14 AD13 AE13 AC13 AF15 AB14 AE16 AD15 AC15 AB15 AC6 AE8 AF13 AF16 AD5 AD8 AC11 AD14 AD16 AC16 AF19 AD17 AB16 AE18 AF20 AD18 AB17 AE19 AC18 Pad Type DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR Power Supply VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
5
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 3 of 12)
Signal MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MWE MRAS MCAS MCS MCKE MCK MCK MODT Package Pin Number AF21 AD19 AF22 AC19 AE21 AD20 AB19 AE22 AD21 AF23 AF24 AD22 AB20 AF17 AF18 AC21 Pad Type DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR LPC Interface (8 Total) LPC_CLK LPC_OE LPC_RW LPC_CS0 LPC_CS1 LPC_CS2 LPC_ACK LPC_AX03 AA4 Y5 AA1 W5 Y3 Y1 AA2 W4 General IO General IO General IO General IO General IO General IO General IO General IO EMB Interface (35 Total) EMB_AX02 EMB_AX01 EMB_AX00 EMB_AD31 EMB_AD30 EMB_AD29 EMB_AD28 EMB_AD27 W3 V5 W2 W1 V4 U5 V3 V2 General IO General IO General IO General IO General IO General IO General IO General IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO -- -- -- -- -- -- -- -- VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO -- -- -- -- -- -- -- -- Power Supply VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 6
Preliminary
Freescale Semiconductor
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 4 of 12)
Signal EMB_AD26 EMB_AD25 EMB_AD24 EMB_AD23 EMB_AD22 EMB_AD21 EMB_AD20 EMB_AD19 EMB_AD18 EMB_AD17 EMB_AD16 EMB_AD15 EMB_AD14 EMB_AD13 EMB_AD12 EMB_AD11 EMB_AD10 EMB_AD09 EMB_AD08 EMB_AD07 EMB_AD06 EMB_AD05 EMB_AD04 EMB_AD03 EMB_AD02 EMB_AD01 EMB_AD00 Package Pin Number V1 U1 U3 T5 T1 T4 T3 R5 T2 R1 R3 P1 P2 P4 P5 P3 N1 N2 N3 N4 M1 M3 M5 L1 L2 L3 L4 Pad Type General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO PATA Interface (9 Total) PATA_CE1 PATA_CE2 PATA_ISOLATE PATA_IOR PATA_IOW PATA_IOCHRDY K1 L5 K3 J1 K5 J2 General IO General IO General IO General IO General IO General IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ATA name: CS0 ATA name: CS1 -- ATA name: DIOR ATA name: DIOW ATA name: IORDY Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
7
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 5 of 12)
Signal PATA_INTRQ PATA_DRQ PATA_DACK Package Pin Number J3 J4 H2 Pad Type General IO General IO General IO NFC Interface (7 Total) NFC_WP NFC_RB NFC_WE NFC_RE NFC_ALE NFC_CLE NFC_CE0 G4 H1 G3 G2 H4 H5 H3 General IO General IO General IO General IO General IO General IO General IO I2C Interface (6 Total) I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA AC23 AD26 AB22 AB23 AC25 AA22 General IO General IO General IO General IO General IO General IO IRQ Interface (2 Total) IRQ0 IRQ1 AC26 AB25 General IO General IO CAN Interface (4 Total) CAN1_RX CAN1_TX CAN2_RX CAN2_TX C19 A18 B19 E16 Analog Input General IO Analog Input General IO J1850 Interface (2 Total) J1850_TX J1850_RX Y22 AA24 General IO General IO SPDIF Interface (3 Total) SPDIF_TXCLK SPDIF_TX SPDIF_RX AB21 AD24 AC24 General IO General IO General IO VDD_IO VDD_IO VDD_IO -- -- -- VDD_IO VDD_IO -- -- VBAT_RTC VDD_IO VBAT_RTC VDD_IO -- -- -- -- VDD_IO VDD_IO -- -- VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO -- -- -- -- -- -- VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO -- -- -- -- -- -- -- Power Supply VDD_IO VDD_IO VDD_IO Notes -- ATA name: DMARQ ATA name: DMACK
MPC5121E/MPC5123 Data Sheet, Rev. 1 8
Preliminary
Freescale Semiconductor
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 6 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
PCI (54 Total) PCI_INTA PCI_RST_OUT PCI_AD00 PCI_AD01 PCI_AD02 PCI_AD03 PCI_AD04 PCI_AD05 PCI_AD06 PCI_AD07 PCI_AD08 PCI_AD09 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 U23 F22 U24 V26 U25 R22 U26 T24 R23 T26 R26 P23 R24 R25 P26 P24 P25 N26 L22 K25 J26 K24 J25 H26 K23 J24 H24 J23 G25 J22 F26 G24 F24 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
9
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 7 of 12)
Signal PCI_AD31 PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1 PCI_REQ2 PCI_GNT0 PCI_GNT1 PCI_GNT2 PCI_CLK Package Pin Number H22 P22 N24 L24 G26 N22 M23 M22 K26 M24 L26 K22 M26 M25 G23 E26 D26 E25 G22 E24 C26 Pad Type PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PSC Interface (61 Total) PSC_MCLK_IN PSC0_0 PSC0_1 PSC0_2 PSC0_3 PSC0_4 PSC1_0 PSC1_1 PSC1_2 PSC1_3 PSC1_4 PSC2_0 C17 D16 A17 E15 C16 B16 C15 A16 E14 A15 D14 C14 General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO -- -- -- -- -- -- -- -- -- -- -- -- Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Notes -- -- -- -- -- -- 4 4 4 4 4 -- 4 4 4 4 4 -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 10
Preliminary
Freescale Semiconductor
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 8 of 12)
Signal PSC2_1 PSC2_2 PSC2_3 PSC2_4 PSC3_0 PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC4_0 PSC4_1 PSC4_2 PSC4_3 PSC4_4 PSC5_0 PSC5_1 PSC5_2 PSC5_3 PSC5_4 PSC6_0 PSC6_1 PSC6_2 PSC6_3 PSC6_4 PSC7_0 PSC7_1 PSC7_2 PSC7_3 PSC7_4 PSC8_0 PSC8_1 PSC8_2 PSC8_3 PSC8_4 PSC9_0 Package Pin Number B14 E13 A14 D13 AF3 AB5 AC4 AD4 AF4 AB1 AA3 AB3 AA5 AC2 AC1 AC3 AD1 AD2 AE3 A11 C10 A10 B9 A9 B8 E10 C8 A8 A7 E9 D8 C7 B6 E8 C6 Pad Type General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Notes -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
11
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 9 of 12)
Signal PSC9_1 PSC9_2 PSC9_3 PSC9_4 PSC10_0 PSC10_1 PSC10_2 PSC10_3 PSC10_4 PSC11_0 PSC11_1 PSC11_2 PSC11_3 PSC11_4 Package Pin Number D7 E7 D6 E6 C13 B13 A13 C12 E12 A12 B11 C11 E11 D11 Pad Type General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO General IO JTAG (5 Total) TCK TDI TDO TMS TRST AB26 Y23 W22 Y25 AA26 General IO General IO General IO General IO General IO Test / Debug (2 Total) TEST CKSTP_OUT W25 Y26 General IO General IO System Control (3 Total) HRESET PORESET SRESET W24 W23 V22 General IO General IO General IO System Clock (2 Total) SYS_XTALI SYS_XTALO V24 W26 Analog Input Analog Output RTC (3 Total) XTALI_RTC XTALO_RTC HIB_MODE C20 A20 D18 Analog Input Analog Output Analog Output VBAT_RTC VBAT_RTC VBAT_RTC Oscillator Input Oscillator Output -- SYS_PLL_AVDD SYS_PLL_AVDD Oscillator Input Oscillator Output VDD_IO VDD_IO VDD_IO 1, 6 2, 6 1, 6 VDD_IO VDD_IO 2, 5 -- VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO 6 3 -- 3 3 Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Notes -- -- -- -- -- -- -- -- -- -- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 12
Preliminary
Freescale Semiconductor
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 10 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
GP Input Only (4 Total) GPIO28 GPIO29 GPIO30 GPIO31 A19 E17 C18 B18 Analog Input Analog Input Analog Input Analog Input DDR Reference Voltage MVREF AB11 Analog Input Voltage Reference for SSTL input pads VBAT_RTC VBAT_RTC VBAT_RTC VBAT_RTC -- -- -- --
USB - PHY without Power and Ground Supplies (7 Total) USB_XTALI USB_XTALO USB_DP USB_DM USB_TPA USB_VBUS USB_UID C24 B24 A23 A22 A24 D21 E19 Analog Input Analog Output Analog IO Analog IO Analog Output Analog IO Analog Input USB digital IOs (2 Total) USB2_VBUS_PWR_FA ULT USB2_DRVVBUS B21 A21 General IO General IO VDD_IO VDD_IO -- -- USB_PLL_PWR3 USB_PLL_PWR3 USB_VDDA USB_VDDA -- -- -- Oscillator Input Oscillator Output -- -- -- -- --
SATA PHY without Power and Ground Supplies (7 Total) SATA_XTALI SATA_XTALO SATA_ANAVIZ SATA_TXN SATA_TXP SATA_RXP SATA_RXN C3 C2 E5 E1 F1 A5 A4 Analog Input Analog Output Analog Output Analog Output Analog Output Analog Input Analog Input SATA_VDDA_3P3 SATA_VDDA_3P3 -- SATA_VDDA_1P2 SATA_VDDA_1P2 SATA_VDDA_1P2 SATA_VDDA_1P2 Oscillator Input Oscillator Output SATA PHY debug output -- -- -- --
Power and Ground Supplies (without SATA PHY and USB PHY) VDD_CORE K10, K11, K12, K13, K14, K15, K16, K17, L10, L17, M10, M17, N10, N17, P10, P17, R10, R17, T10, T17, U10, U11, U12, U13, U14, U15, U16, U17 Power -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
13
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 11 of 12)
Signal VDD_IO Package Pin Number B10, B15, B25, D10, D15, F11, F13, F14, F19, F23, F25, H21, J5, K2, K4, L23, L25, N6, N21, P6, P21, R2, R4, T23, T25, W6, W21, Y2, Y4, AA23, AA25, AE1, AE2, AE24, AE25, AF2, AF25 AA8, AA13, AA14, AB18, AC5, AC10, AC14, AC20, AD9, AE5, AE10, AE15, AE20 A2, A3, A25, B1,B2, B3, B5, B7, B12, B17, B20, B22, B26, C1, C4, C23, C25, D2, D12, D17, D24, D25, E18, F2, F3, F4, F5, F6, F8, F10, F16, F17, F21, G5, H6, H23, H25, K6, K21, L6, L11, L12, L13, L14, L15, L16, L21, M2, M4, M11, M12, M13, M14, M15, M16, N5, N11, N12, N13, N14, N15, N16, N23, N25, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T6, T11, T12, T13, T14, T15, T16, T21, U2, U4, U6, U21, V23, V25, Y24, AA6, AA10, AA11, AA16, AA17, AA21, AB2, AB4, AB10, AB24, AC8, AC12, AC17, AC22, AD3, AD25, AE7, AE12, AE17, AE23, AE26 T22 U22 AA19 AD23 D19 Pad Type Power Power Supply -- Notes --
VDD_MEM_IO
Power
--
--
VSS
Ground
--
--
VSS
Ground
--
--
SYS_PLL_AVDD SYS_PLL_AVSS CORE_PLL_AVDD CORE_PLL_AVSS VBAT_RTC
Analog Power Analog Ground Analog Power Analog Ground Power
-- -- -- -- --
-- -- -- -- --
MPC5121E/MPC5123 Data Sheet, Rev. 1 14
Preliminary
Freescale Semiconductor
Pin Assignments
Table 3. MPC5121E/MPC5123 TE-PBGA Pinout Listing (Sheet 12 of 12)
Signal AVDD_FUSEWR AVDD_FUSERD MVTT0 MVTT1 MVTT2 MVTT3 Package Pin Number C9 D9 AB7 AF9 AE11 AE14 Pad Type Power Power Analog Input Analog Input Analog Input Analog Input Power Supply -- -- Notes -- --
SSTL(DDR2) Termination (ODT) Voltage SSTL(DDR2) Termination (ODT) Voltage SSTL(DDR2) Termination (ODT) Voltage SSTL(DDR2) Termination (ODT) Voltage
Power and Ground Supplies (USB PHY) USB_PLL_GND USB_PLL_PWR3 USB_RREF USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA E23 D23 E22 B23 D22 C22, E20, E21 C21, D20 Analog Ground Analog Power Analog Power Analog Ground Analog Power Analog Ground Analog Power -- -- -- -- -- -- -- -- -- -- -- -- -- --
Power and Ground Supplies (SATA PHY) SATA_RESREF SATA_VDDA_3P3 SATA_VDDA_1P2 SATA_VDDA_VREG SATA_PLL_VDDA1P2 SATA_PLL_VSSA SATA_RX_VSSA SATA_TX_VSSA E4 D4 C5, D1, E2 D5 E3 D3 A6, B4 G1 Analog Power Analog Power Analog Power Analog Power Analog Power Analog Ground Analog Ground Analog Ground -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1) This pin is an input or open-drain output. This pin can not be configured. An external pull-up resistor is required. 2) This pin is an input only. This pin can not be configured. 3) These JTAG pins have internal pull-up P-FETs. This pin can not be configured. 4) This pins should have an external pull-up resistor. Follow PCI specification and see System Design Information. 5) This test pin must be tied to VSS. 6) This pin contains an enabled internal schmitt-trigger.
NOTE
This table indicates only the pins with permananently enabled internal pull-up, pull-down, or schmitt-trigger. Most of the digital I/O pins can be configured to enable internal pull-up, pull-down, or schmitt-trigger. See MPC5121E Reference Manual, IO Control chapter.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
15
Electrical and Thermal Characteristics
3
3.1
3.1.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
Absolute Maximum Ratings
The tables in this section describe the MPC5121E/MPC5123 DC Electrical characteristics. Table 4 gives the absolute maximum ratings. Table 4. Absolute Maximum Ratings1
Characteristic Supply voltage - e300 core and peripheral logic Supply voltage - I/O buffers Supply voltage - System APLL, System Oscillator Supply voltage - e300 APLL Supply voltage - RTC (Hibernation) Supply voltage - FUSE Programming Supply voltage - FUSE Reading Supply voltage - SATA PHY analog Supply voltage - SATA PHY voltage regulator Supply voltage - SATA PHY Tx/Rx Supply voltage - SATA PHY PLL Supply voltage - USB PHY PLL and OSC Supply voltage - USB PHY transceiver Supply voltage - USB PHY bandgap bias Input voltage - USB PHY cable Input voltage (VDD_IO) Input voltage (VDD_MEM_IO) Input voltage (VBAT_RTC) Input voltage overshoot Input voltage undershoot Storage temperature range
1
Sym VDD_CORE VDD_IO, VDD_MEM_IO SYS_PLL_AVDD CORE_PLL_AVDD VBAT_RTC AVDD_FUSEWR AVDD_FUSERD SATA_VDDA_3P3 SATA_VDDA_VREG SATA_VDDA_1P2 SATA_PLL_VDDA1P2 USB_PLL_PWR3 USB_VDDA USB_VDDA_BIAS USB_VBUS Vin Vin Vin Vinos Vinus Tstg
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -55
Max 1.47 3.6 3.6 3.6 3.6 3.6 3.6 3.6 2.6 1.47 1.47 3.6 3.6 3.6 3.6 VDD_IO + 0.3 VDD_MEM_IO + 0.3 VBAT_RTC + 0.3 1 1 150
Unit V V V V V V V V V V V V V V V V V V V V
oC
SpecID D1.1 D1.2 D1.3 D1.4 D1.5 D1.6 D1.7 D1.8 D1.9 D1.10 D1.11 D1.12 D1.13 D1.14 D1.15 D1.16 D1.17 D1.18 D1.19 D1.20 D1.21
Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage.
MPC5121E/MPC5123 Data Sheet, Rev. 1 16
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.1.2
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Characteristic Sym VDD_CORE Min1 1.33 1.08 VDD_IO VDD_MEM_IODDR VDD_MEM_IODDR2
VDD_MEM_IOLPDDR
3)
Table 5 gives the recommended operating conditions.
Typ 1.4
Max1 1.47
Unit V V V V V V V V V V V V V V V V V V V V V V V V
o
SpecID D2.1 D2.2 D2.3 D2.4 D2.5 D2.6 D2.7 D2.8 D2.9 D2.10 D2.11 D2.12 D2.13 D2.14 D2.15 D2.16 D2.17 D2.18 D2.19 D2.20 D2.21 D2.22 D2.23 D2.24 D2.25
Supply voltage - e300 core and peripheral logic State Retention voltage - e300 core and peripheral logic 2 Supply voltage - standard I/O buffers Supply voltage - memory I/O buffers (DDR) Supply voltage - memory I/O buffers (DDR2, LPDDR) Input Reference Voltage (DDR/DDR2) Termination Voltage (DDR2) Supply voltage - System APLL, System Oscillator Supply voltage - e300 APLL Supply voltage - RTC (Hibernation) Supply voltage - FUSE Programming Supply voltage - FUSE Reading Supply voltage - SATA PHY analog and OSC Supply voltage - SATA PHY voltage regulator Supply voltage - SATA PHY Tx/Rx Supply voltage - SATA PHY PLL Supply voltage - USB PHY PLL and OSC Supply voltage - USB PHY transceiver Supply voltage - USB PHY bandgap bias Input voltage - USB PHY cable Input voltage - standard I/O buffers Input voltage - memory I/O buffers (DDR) Input voltage - memory I/O buffers (DDR2) Input voltage - memory I/O buffers (LPDDR) Ambient operating temperature range
-- 3.3 2.5 1.8
-- 3.6 2.7 1.9
3.0 2.3 1.7
MVREF MVTT SYS_PLL_AVDD CORE_PLL_AVDD VBAT_RTC AVDD_FUSEWR AVDD_FUSERD SATA_VDDA_3P3 SATA_VDDA_VREG SATA_VDDA_1P2
SATA_PLL_VDDA1P2
0.49*VDD_M 0.50*VDD_M 0.51*VDD_ EM_IO EM_IO MEM_IO MVREF-0.04 3.0 3.0 3.0 3.3 3.0 3.0 1.7 1.14 1.33 3.0 3.0 3.0 1.4 0 0 0 0 -40 1.2 1.4 3.3 3.3 3.3 -- -- -- -- -- -- 3.3 3.3 MVREF 3.3 3.3 3.3 MVREF+ 0.04 3.6 3.6 3.6 3.6 3.6 3.6 2.6 1.47 1.47 3.6 3.6 3.6 3.6 VDD_IO VDD_MEM _IODDR VDD_MEM _IODDR2 VDD_MEM _IOLPDR +85
USB_PLL_PWR3 USB_VDDA USB_VDDA_BIAS USB_VBUS Vin VinDDR VinDDR2 VinLPDDR TA
C
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
17
Electrical and Thermal Characteristics
1
These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 The State Retention voltage can be applied to VDD_CORE after the device is placed in Deep-Sleep mode.
3.1.3
DC Electrical Specifications
Table 6. DC Electrical Specifications
Table 6 gives the DC Electrical characteristics for the MPC5121E/MPC5123 at recommended operating conditions.
Characteristic Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage
Condition Input type = TTL VDD_IO Input type = TTL VDD_MEM_IODDR Input type = TTL VDD_MEM_IODDR2 Input type = TTL VDD_MEM_IOLPDDR Input type = PCI VDD_IO Input type = SCHMITT VDD_IO SYS_XTALI crystal mode bypass mode2
1
Sym VIH VIH VIH VIH VIH VIH CVIH SVIH UVIH RVIH VIL VIL VIL VIL VIL VIL CVIL SVIL UVIL RVIL
Min 0.51*VDD_IO MVREF+0.15 MVREF+0.125 0.7*VDD_IO_MEML
PDDR
Max -- -- -- -- -- -- -- -- -- -- 0.42*VDD_IO MVREF-0.15 MVREF-0.125 0.3*VDD_IO_MEML
PDDR
Unit SpecID V V V V V V V V V V V V V V V V V V V V D3.1 D3.2 D3.3 D3.4 D3.5 D3.6 D3.7 D3.8 D3.9 D3.10 D3.11 D3.12 D3.13 D3.14 D3.15 D3.16 D3.17 D3.18 D3.19 D3.20
0.5*VDD_IO 0.65*VDD_IO Vxtal+0.4V (VDD_IO/2)+0.4V Vxtal+0.4V (VDD_IO/2)+0.4V Vxtal+0.4V (VDD_IO/2)+0.4V (VBAT_RTC/5)+0.5V (VBAT_RTC/2)+0.4V -- -- -- -- -- -- -- -- -- --
SATA_XTALI crystal mode bypass mode USB_XTALI crystal mode bypass mode RTC_XTALI crystal mode3 bypass mode4 Input type = TTL VDD_IO Input type = TTL VDD_MEM_IODDR Input type = TTL VDD_MEM_IODDR2 Input type = TTL VDD_MEM_IOLPDDR Input type = PCI VDD_IO Input type = SCHMITT VDD_IO SYS_XTALI crystal mode bypass mode SATA_XTALI crystal mode bypass mode USB_XTALI crystal mode bypass mode RTC_XTALI crystal mode bypass mode
0.3*VDD_IO 0.35*VDD_IO Vxtal-0.4V (VDD_IO/2)-0.4V Vxtal-0.4V (VDD_IO/2)-0.4V Vxtal-0.4V (VDD_IO/2)-0.4V (VBAT_RTC/5)-0.5V (VBAT_RTC/2)-0.4V
MPC5121E/MPC5123 Data Sheet, Rev. 1 18
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 6. DC Electrical Specifications (continued)
Characteristic Input leakage current Condition Vin = 0 or VDD_IO/VDD_MEM_IODDR/2 (depending on input type)5 Sym IIN Min -2.5 Max 2.5 Unit SpecID A D3.21
Input leakage current SYS_XTAL_IN Vin = 0 or VDD_IO Input leakage current RTC_XTAL_IN Vin = 0 or VDD_IO Input current, pullup resistor6 Input current, pulldown resistor 8 Output high voltage Output high voltage Output high voltage Output high voltage Output low voltage Output low voltage Output low voltage Output low voltage Differential cross point voltage (DDR MCK/MCK) DC Injection Current Per Pin8 Input Capacitance (digital pins) Input Capacitance (analog pins) On Die Termination (DDR2)
1
IIN IIN IINpu IINpd VOH VOHDDR
-- -- 25 25 0.8*VDD_IO 1.94
20 1.0 150 150 -- -- -- -- 0.2*VDD_IO 0.36 0.28 0.28
A A A A V V V V V V V V V
D3.22 D3.23 D3.24 D3.25 D3.26 D3.27 D3.28 D3.28 D3.30 D3.31 D3.32 D3.33 D3.34
PULLUP VDD_IO Vin = VIL PULLDOWN VDD_IO Vin = VIH IOH is driver dependent7 VDD_IO IOH is driver dependent7 VDD_MEM_IODDR IOH is driver dependent7 VDD_MEM_IODDR2 IOH is driver dependent7 VDD_MEM_IOLPDDR IOL is driver dependent7 VDD_IO IOL is driver dependent7 VDD_MEM_IODDR IOL is driver dependent7 VDD_MEM_IODDR2 IOL is driver dependent7 VDD_MEM_IOLPDDR --
VOHDDR2 VDD_MEM_IO-0.28 VOHLPDD VDD_MEM_IO-0.28
R
VOL VOLDDR VOLDDR2 VOLLPDD
R
-- -- -- --
VOXMCK 0.5*VDD_MEM_IO - 0.5*VDD_MEM_IO 0.125 +0.125 ICS Cin Cin RODT -1.0 -- -- 120 1.0 7 10 180
-- -- -- --
mA pF pF
D3.35 D3.36 D3.37 D3.38
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vextal - Vxtal - 400mV criteria has to be met for oscillator's comparator to produce output clock. 2 This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass mode. In that case, drive only the EXTAL pin not connecting anything to other pin for the oscillator's comparator to produce output clock. 3 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, drive one of the XTAL_IN or XTAL_OUT pins not connecting anything to other pin for the oscillator's comparator to produce output clock.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
19
Electrical and Thermal Characteristics
4
5 6 7 8
This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass mode. In that case, drive only the xtal_in pin not connecting anything to other pin for the oscillator's comparator to produce output clock. Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. Pullup current is measured at VIL and pulldown current is measured at VIH. See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 3. All injection current is transferred to VDD_IO/VDD_MEM_IO. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation.
Table 7. I/O Pads - Drive Current, Slew Rate
Pad Type General IO Supply Voltage VDD_IO = 3.3V Drive Select/Slew Rate Control configuration 3 (11) configuration 2 (10) configuration 1 (01) configuration 0 (00) DDR VDD_MEM_IO = 2.5V (DDR) configuration 3 (011) VDD_MEM_IO = 1.8V (LPDDR) VDD_MEM_IO = 1.8V (DDR2) PCI VDD_IO = 3.3V configuration 0 (000) configuration 1 (001) configuration 2 (010) configuration 6 (110) configuration 1 (1) configuration 0 (0)
1
Rise time max (ns) 1.4 9.8 19 140 2 1
Fall time max (ns) 1.6 12 24 183 2 1
Current Current SpecID Ioh (mA) Iol (mA) 35 35 D3.41 D3.42 D3.43 D3.44 16.2 4.6 8.1 16.2 4.6 8.1 5.3 13.4 17 D3.45 D3.46 D3.47 D3.48 D3.49 D3.50 D3.51
1
1
5.3 13.4
1.4 2
1.4 2
11
Notes: 1. General IO - Rise and Fall Times at Drive load 50pF. 2. PCI - Rise and Fall Times at Drive load 10pF. 3. DDR - for LPDDR/Mobile-DDR, slew rate is measured between 20 % VDD_IO_MEM and 80 % VDD_IO_MEM 4. DDR - for DDR, DDR2, rising signals, slew rate is measured between VDD_IO_MEM * 0.5 and ViHAC. For falling signals, slew rate is measured between VDD_IO_MEM * 0.5 and ViLAC. 5. DDR - Rise and Fall Times terminated at the destination with 50 ohm to MVTT (0.5*VDD_IO_MEM) with 4pF, representing the DDR input capacitance.
3.1.4
Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or VDD). Table 10 gives package thermal characteristics for this device.
MPC5121E/MPC5123 Data Sheet, Rev. 1 20
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 8. ESD and Latch-Up Protection Characteristics
Sym VHBM VMM VCDM Rating Human Body Model (HBM) - JEDEC JESD22-A114-B Machine Model (MM) - JEDEC JESD22-A115 Charge Device Model (CDM) - JEDEC JESD22-C101 Min 2000 200 500 Max -- -- -- Unit V V V SpecID D4.1 D4.2 D4.3
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
21
Electrical and Thermal Characteristics
3.1.5
Power Dissipation
Power dissipation of the MPC5121E/MPC5123 is caused by 4 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD), the dissipation of the IO logic (supplied by VDD_MEM_IO and VDD_IO) and the dissipation of the PHYs (supplied by own supplies). Table 9 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each application case using the following formula: P IO = P IOint +
N x C x VDD_IO
M
2
xf
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5121E/MPC5123 processor must not exceed the value, which would cause the maximum junction temperature to be exceeded. P total = P core + P analog + P IO + PPHYs Table 9. Power Dissipation
Core Power Supply (VDD_CORE) High-Performance Mode e300 = 300 MHz, CSB = 200 MHz Operational
1, 1,
Eqn. 2
SpecID Unit
800 1 20
mW mW uW
D5.1 D5.2 D5.3
Deep-Sleep Hibernation
PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD) Typical 25 mW D5.4
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO) Typical 300 mW D5.5
PHY Power Supplies (USB_VDDA, SATA_VDDA) Typical
1
200
mW
D5.6
Typical core power is measured at VDD_CORE = 1.4 V, Tj = 25 C.
NOTE
The maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations. The worst case power consumption could reach a maximum of 2000 mW.
MPC5121E/MPC5123 Data Sheet, Rev. 1 22
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.1.6
Thermal Characteristics
Table 10. Thermal Resistance Data
Rating Board Layers Sym RJA RJMA RJMA RJMA RJB RJC JT Value 30 22 24 19 14 8 2 Unit C/W C/W C/W C/W C/W C/W C/W SpecID D6.1 D6.2 D6.3 D6.4 D6.5 D6.6 D6.7
Junction to Ambient Natural Single layer board (1s) Convection1,2 Junction to Ambient Natural Four layer board (2s2p) Convection1,3 Junction to Ambient (@200 ft/min)1,3 Junction to Ambient (@200 ft/min)1,3 Junction to Board4 Junction to Case
5
Single layer board (1s) Four layer board (2s2p) -- -- Natural Convection
Junction to Package Top6
1
2 3 4 5 6
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.1.6.1
Heat Dissipation
TJ = TA +(R JA x PD )
An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: Eqn. 3
where: TA = ambient temperature for the package (C) R JA = junction to ambient thermal resistance (C/W) PD = power dissipation in package (W) The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
23
Electrical and Thermal Characteristics
R JA = R JC +R CA where: R JA = junction to ambient thermal resistance (C/W) R JC = junction to case thermal resistance (C/W) R CA = case to ambient thermal resistance (C/W)
Eqn. 4
R JC is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient thermal resistance, R CA. For instance, you can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT +( JT x PD ) where: TT = thermocouple temperature on top of package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. Eqn. 5
3.2
Oscillator and PLL Electrical Characteristics
The MPC5121E/MPC5123 System requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent Real-Time Clock (RTC) system. The MPC5121E/MPC5123 clock generation uses two phase locked loop (PLL) blocks. * The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.
*
The USB PHY contains its own oscillator with the input USB_XTALI and an embedded PLL. The SATA PHY contains its own oscillator with the input SATA_XTALI and an embedded PLL.
MPC5121E/MPC5123 Data Sheet, Rev. 1 24
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.2.1
System Oscillator Electrical Characteristics
Table 11. System Oscillator Electrical Characteristics
Characteristic SYS_XTAL frequency Sym fsys_xtal Min 15.6 Typical 33.3 Max 35.0 Unit MHz SpecID O1.1
The System Oscillator can work in Oscillator mode or in bypass mode to support an external input Clock as clock reference.
t CYCLE t DUTY t DUTY t RISE CV IH SYS_XTAL_I CLK VM VM VM CV IL t FALL
Figure 2. Timing Diagram--SYS_XTAL_IN Table 12. SYS_XTAL_IN Timing
Sym t CYCLE t RISE t FALL t DUTY
1
Description SYS_XTALI cycle time.1,2
Min 64.1 1 1 )5 40
Max 28.57 4 4 60
Units ns ns ns %
SpecID O.1.2 O.1.3 O.1.4 O.1.5
SYS_XTALI rise time.3 SYS_XTALI fall time.4
SYS_XTALI duty cycle (measured at V M
2 3 4 5
The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5121E/MPC5123 Reference Manual. The MIN/Max cycle times are calculated using 1/fsys_xtal (MIN/MAX) where the fsys_xtal (MIN/MAX) (15.6/35 MHz) are taken from Table 11. Rise time is measured from 20% of vdd to 80% of vdd. Fall time is measured from 20% of vdd to 80% of vdd. SYS_XTALI duty cycle is measured at V M.
3.2.2
RTC Oscillator Electrical Characteristics
Table 13. RTC Oscillator Electrical Characteristics
Characteristic RTC_XTAL frequency Sym frtc_xtal Min -- Typical 32.768 Max -- Unit kHz SpecID O2.1
3.2.3
System PLL Electrical Characteristics
Table 14. System PLL Specifications
Characteristic Sys PLL input clock frequency1 Sys PLL input clock jitter
2
Sym fsys_xtal tjitter
Min 16 --
Typical 33.3 --
Max 67 10
Unit MHz ps
SpecID O3.1 O3.2
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
25
Electrical and Thermal Characteristics
Table 14. System PLL Specifications
Characteristic Sys PLL VCO frequency1 Sys PLL VCO output jitter (Dj), peak to peak / cycle Sys PLL VCO output jitter (Rj), rms 1 sigma Sys PLL relock time - after power up 3 Sys PLL relock time - when power was on4
1
Sym fVCOsys fVCOjitterDj fVCOjitterRj tlock1 tlock2
Min 400 -- -- -- --
Typical -- -- -- -- --
Max 800 40 12 200 170
Unit MHz ps ps s s
SpecID O3.3 O3.4 O3.5 O3.6 O3.7
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter - short term and long term combined. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. 4 PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently re-enabled during sleep modes.
3.2.4
e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 15. e300 PLL Specifications
Characteristic e300 frequency1 Sym fcore fVCOcore fCSB_CLK tCSB_CLK tlock Min 50 400 50 5 -- Typical -- -- -- -- -- Max 400 800 200 20 200 Unit MHz MHz MHz ns s SpecID O4.1 O4.3 O4.4 O4.5 O4.6
e300 PLL VCO frequency1 e300 PLL input clock frequency e300 PLL input clock cycle time e300 PLL relock time
1 2
The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 16. 2 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
MPC5121E/MPC5123 Data Sheet, Rev. 1 26
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3
3.3.1
* * * * * * * * * * * *
AC Electrical Characteristics
Overview
AC Operating Frequency Data Resets External Interrupts SDRAM (DDR) PCI LPC NFC PATA SATA PHY FEC USB ULPI On-Chip USB PHY * * * * * * * * * * * * SDHC DIU SPDIF CAN I2C J1850 PSC GPIOs and Timers Fusebox IEEE 1149.1 (JTAG) VIU
Hyperlinks to the indicated timing specification sections are provided below.
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows: * * * * TA = -40 to 85oC VDD_CORE = 1.33 to 1.47 V VDD_IO = 3.0 to 3.6 V Input conditions: All Inputs: tr, tf <= 1 ns Output Loading: All Outputs: 50 pF
3.3.2
AC Operating Frequency Data
Table 16. Clock Frequencies
Min e300 Processor Core SDRAM Clock CSB Bus Clock IP Bus Clock PCI Clock LPC Clock 200 28.6 50.0 8.3 4.43 2.08 Max 400 200 200 83 66 83 Units MHz MHz MHz MHz MHz MHz SpecID A1.1 A1.2 A1.3 A1.4 A1.5 A1.6
Table 16 provides the operating frequency information for the MPC5121E/MPC5123.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
27
Electrical and Thermal Characteristics
Table 16. Clock Frequencies (continued)
Min NFC Clock DIU Clock SDHC Clock MBX Clock 2.08 0.78 0.78 6.25 Max 83 100 66.6 100 Units MHz MHz MHz MHz SpecID A1.7 A1.8 A1.9 A1.10
NOTES: 1. The SYS_XTAL_IN frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK, frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The values are valid for the user-operation mode. There can be deviations for test modes. 3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency limitation. 4.The DDR data rate is 2x the DDR memory bus frequency. See the MPC5121E Reference Manual for more information on the clock subsystem.
3.3.3
* * *
Resets
PORESET - Power on Reset HRESET - Hard Reset SRESET - Software Reset
The MPC5121E/MPC5123 has three reset pins:
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5121E/MPC5123 inputs, as specified in the DC Electrical Specifications section. As long as VDD is not stable the HRESET output is not stable. Table 17. Reset Rise / Fall Timing
Description PORESET1 fall time PORESET rise time HRESET
2,3
Min -- -- -- -- -- --
Max 1 1 1 1 1 1
Unit ms ms ms ms ms ms
SpecID A3.4 A3.5 A3.6 A3.7 A3.8 A3.9
fall time
HRESET rise time SRESET fall time SRESET rise time
1
Make sure that the PORESET does not carry any glitches. The MPC5121E/MPC5123 has no filter to prevent them from getting into the chip. 2 HRESET and SRESET must have a monotonous rise time. 3 The assertion of HRESET becomes active at Power on Reset without any SYS_XTAL clock.
The timing relationship can be seen below.
MPC5121E/MPC5123 Data Sheet, Rev. 1 28
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
SYS_XTALI PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF RST_CONF[31:0] ADDR[31:0] tH_POR_CONF tEXEC
Figure 3. Power-Up Behavior
SYS_XTALI tPORHold PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF RST_CONF[31:0] ADDR[31:0] tH_POR_CONF tEXEC
Figure 4. Power-On Reset Behavior
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
29
Electrical and Thermal Characteristics
SYS_XTALI
PORESET
tHRHOLD tHRVAL
HRESET tSRVAL SRESET tHR_SR_Delay RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF tEXEC
Figure 5. HRESET Behavior
SYS_XTALI
PORESET
HRESET
tSRHOLD tSRMIN
SRESET tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF
Figure 6. SRESET Behavior Table 18. Reset Timing
Symbol tPORHOLD tHRVAL tSRVAL tEXEC Description Time PORESET must be held low before a qualified reset occurs Time HRESET is asserted after a qualified reset occurs Time SRESET is asserted after assertion of HRESET Time between SRESET assertion and first core instruction fetch Value SYS_XTALI 4 cycles 26810 cycles 32 cycles 4 cycles SpecID A3.10 A3.11 A3.12 A3.13
MPC5121E/MPC5123 Data Sheet, Rev. 1 30
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 18. Reset Timing (continued)
Symbol tS_POR_CONF tH_POR_CONF tHR_SR_DELAY tHRHOLD tSRHOLD tSRMIN Description Reset configuration setup time before assertion of PORESET Reset configuration hold time after assertion of PORESET Time from falling edge of HRESET to falling edge of SRESET Time HRESET must be held low before a qualified reset occurs Time SRESET must be held low before a qualified reset occurs Time SRESET is asserted after it has been qualified Value SYS_XTALI 1 cycle 1 cycle 4 cycles 4 cycles 4 cycles 1 cycles SpecID A3.14 A3.15 A3.16 A3.17 A3.18 A3.19
3.3.4
* * *
External Interrupts
IRQ interrupts GPIO interrupts with simple interrupt capability (not available in power-down mode) WakeUp interrupts Table 19. IPIC Input AC Timing Specifications1
Description IPIC inputs - minimum pulse witdh
1
The MPC5121E/MPC5123 provides three different kinds of external interrupts:
Symbol tPICWID
Min 2T
Unit ns
SpecID A4.1
T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus freqency of 83 MHz).
IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode.
3.3.5
* * *
SDRAM (DDR)
DDR-1 (SSTL_2 class II interface) DDR-2 (SSTL_18 interface) LPDDR/Mobile-DDR (1.8V I/O supply voltage) -- JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, MAY 2006 -- JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005 -- JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006
The MPC5121E/MPC5123 memory controller supports three types of DDR devices:
JEDEC standards define the minimum set of requirements for complient memory devices:
The MPC5121E/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR: * * full drive strength half drive strengh (intended for ligther loads or point-to-point environments)
The MPC5121E/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical Characteristics.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
31
Electrical and Thermal Characteristics
3.3.5.1
DDR and DDR2 SDRAM AC Timing Specifications
Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications
At recommended operating conditions with VDD_MEM_IO of 5% Parameter Symbol tCK VIX-AC tCH tCL tDQSS tOS(base) tOH(base) tDS1(base) tDH1(base) tDQSQ tDQSEN Min 5000 Max -- Unit ps V tCK tCK tCK ps ps ps ps ps ps 1 1,3 1,3 2,3 2,3 2,3 2,3 2,3 3 1,2,3,4,5 Notes SpecID A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 A5.8 A5.9 A5.10 A5.11
Clock cycle time, CL=x MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge Address and control output hold time relative to MCK rising edge DQ and DM output setup time relative to DQS DQ and DM output hold time relative to DQS DQS-DQ skew for DQS and associated DQ inputs DQS window start position related to CAS read command
VDD_IO_MEM*0.5 VDD_IO_MEM * 0.5 - 0.1 + 0.1 0.47 0.47 -0.25 tCK/2 - 750 tCK/2 - 750 tCK/4 - 500 tCK/4 - 500 - tCK/4 - 600 TBD 0.53 0.53 0.25 -- -- -- -- tCK/4 - 600 TBD
Notes: 1. Measured with clock pin loaded with differential 100 ohm termination resistor. 2. Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDD_IO_MEM/2. 3. All transitions measured at mid-supply (VDD_IO_MEM/2) 4. In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5. Window position is given for tDQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly.
Figure 7 shows the DDR SDRAM write timing.
MPC5121E/MPC5123 Data Sheet, Rev. 1 32
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
MCK
DQS(out) tDQSS
DQ, DM(out) tDS tDH
Figure 7. DDR Write Timing Figure and Figure 9 shows the DDR SDRAM read timing
DQS(in)
Any DQ(in) tDQSQ tDQSQ tDQSQ
Figure 8. DDR Read Timing, DQ vs DQS
MCK
Command Read Address t t OS OH
DQS(in) t DQSEN(MIN) t DQSEN
Figure 9. DDR Read Timing, DQSEN Figure 10 provides the AC test load for the DDR bus.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
33
Electrical and Thermal Characteristics
Output
Z0 = 50
VDD_MEM_IO/2 RL = 50
Figure 10. DDR AC Test Load
3.3.6
PCI
The PCI interface on the MPC5121E/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations. See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors. The PCI_CLK is used as output clock, the MPC5121E/MPC5123 is a PCI host device only. Figure 11 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications.
t cyc t high 0.6Vcc PCI CLK 0.5Vcc 0.4Vcc 0.3Vcc 0.4Vcc, p-to-p (minimum) t low
0.2Vcc
Figure 11. PCI CLK Waveform
2
Table 21. PCI CLK Specifications
66 MHz1 Sym tcyc thigh t low --
1
33 MHz Units SpecID Min 30 11 11 1 Max -- -- -- 4 ns ns ns V/ns A6.1 A6.2 A6.3 A6.4
Description PCI CLK Cycle Time1,3 PCI CLK High Time PCI CLK Low Time PCI CLK Slew Rate2
Min2 15 6 6 1.5
Max 30 -- -- 4
In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz. 2 Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 11. 3 The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
MPC5121E/MPC5123 Data Sheet, Rev. 1 34
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 22. PCI Timing Parameters1
66 MHz Sym tval Description CLK to Signal Valid Delay - bused signals1,2,3 Min2 2 2 2 Max 6 6 -- 14 3 5 0 -- -- -- 7 10,12 0 33 MHz Units Min 2 2 2 Max 11 12 -- 28 -- -- -- ns ns ns ns ns ns ns A6.5 A6.6 A6.7 A6.8 A6.9 A6.10 A6.11 SpecID
tval(ptp) CLK to Signal Valid Delay - point to point1,2,3 t on t off t su Float to Active Delay1 Active to Float Delay
1
Input Setup Time to CLK - bused signals3,4
t su(ptp) Input Setup Time to CLK - point to point3,4 th
1
Input Hold Time from CLK4
See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2 Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification. 3 REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. 4 See the timing measurement conditions in the PCI Local Bus Specification.
For Measurement and Test Conditions, see the PCI Local Bus Specification.
3.3.7
LPC
The Local Plus Bus is the external bus interface of the MPC5121E/MPC5123. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK. The maximum bus frequency is 83 MHz. Definition of Acronyms and Terms: WS = Wait State DC = Dead Cycle HC = Hold Cycle DS = Data Size in Bytes BBT = Burst Bytes per Transfer AL = Address latch enable Length ALT = Chip select/Address Latch Timing tLPCck = LPC clock period
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
35
Electrical and Thermal Characteristics
Table 23. LPC Timing
Sym tOD Description CS[x], ADDR, R/W, TSIZ, DATA (wr), TS, OE valid after LPC CLK (Output Delay related to LPC CLK) non-muxed non-Burst CS[x] pulse width ADDR, R/W, TSIZ, DATA (wr) valid before CS[x] assertion OE assertion after CS[x] assertion ADDR, R/W, TSIZ, Data (wr) hold after CS[x] negation TS pulse width DATA (rd) setup before LPC CLK DATA (rd) input hold Min 0 Max 5 Units SpecID ns A7.1
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16
(2+WS)*tLPCck tLPCck-tOD tLPCck-tOD tLPCck-tOD tLPCck 4 0
(2+WS)*tLPCck tLPCck+tOD tLPCck+tOD (HC+1)*tLPCck+tOD tLPCck (DC+1)*tLPCck (2+WS+BBT*(8/DS))*tLPCck (BBT*(8/DS))*tLPCck (2+WS)*tLPCck (2.5+WS+BBT*(8/DS)) *tLPCck (HC+0.5)*tLPCck+tOD (2.5+WS)*tLPCck+tOD 0.5*tLPCck+tOD
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A7.2 A7.3 A7.4 A7.5 A7.6 A7.7 A7.8 A7.9 A7.10 A7.11 A7.12 A7.13 A7.14 A7.15 A7.16 A7.17
non-muxed read Burst CS[x] pulse width (2+WS+BBT*(8/DS))*tLPCck Burst ACK pulse width Burst DATA (rd) input hold read Burst ACK assertion after CS[x] assertion non-muxed write Burst CS[x] pulse width write Burst ADDR, R/W, TSIZ, DATA (wr) hold after CS[x] negation write Burst ACK assertion after CS[x] assertion write Burst DATA valid non-Muxed Mode: asynchronous write Burst ADDR valid before write DATA valid MUXed Mode: ADDR cycle MUXed Mode: ALE cycle non-MUXed Mode Page Burst: ADDR cycle non-MUXed Mode Page Burst: Burst DATA (rd) input setup before next ADDR cycle non-MUXed Mode Page Burst: Burst DATA (rd) input hold after next ADDR cycle MUXed Mode: non-Burst CS[x] pulse width (BBT*(8/DS))*tLPCck 0 (2+WS)*tLPCck (2.5+WS+BBT*(8/DS)) *tLPCck 0.5*tLPCck-tOD (2.5+WS)*tLPCck-tOD tLPCck-tOD 0.5*tLPCck-tOD
t17 t18 t19 t20
AL*2*tLPCck-tOD AL*tLPCck tLPCck-tOD tOD + t6
AL*2*tLPCck AL*tLPCck tLPCck
ns ns ns ns
A7.18 A7.19 A7.20 A7.21
-- 0 -- (ALT*(AL*2)+2+WS)*tLPCck (ALT*(AL*2)+2+WS)*tLPCck ns A7.23 ns A7.22
t21
t22
MPC5121E/MPC5123 Data Sheet, Rev. 1 36
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 23. LPC Timing (continued)
Sym t23 t24 Description MUXed Mode: read Burst CS[x] pulse width MUXed Mode: write Burst CS[x] pulse width Min Max Units SpecID ns ns A7.24 A7.25
(ALT*(AL*2)+2+WS+BBT*(8/ (ALT*(AL*2)+2+WS+BBT*(8/ DS))*tLPCck DS))*tLPCck (ALT*(AL*2)+2.5+WS+BBT*( (ALT*(AL*2)+2.5+WS+BBT*( 8/DS))*tLPCck 8/DS))*tLPCck
3.3.7.1
3.3.7.1.1
Non-MUXed Mode
Non-Muxed non-Burst Mode
tLPCck LPC CLK t1 CS[x] ADDR t2 OE R/W DATA (wr) t6 DATA (rd) t7 t3 t4
ACK t5 TS TSIZ[1:0]
Figure 12. Timing Diagram - Non-MUXed non-Burst Mode
NOTE
ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
37
Electrical and Thermal Characteristics
3.3.7.1.2
LPC_CLK
Non-Muxed Synchronous Read Burst Mode
t8 CS[x] ADDR t5 TS t3 OE R/W t6 DATA (rd) t11 ACK t9 t10 t7 t2 Valid Address t4
Figure 13. Timing Diagram - Non-MUXed Synchronous Read Burst Mode
3.3.7.1.3
LPC_CLK
Non-Muxed Synchronous Write Burst Mode
t12 CS[x] ADDR t5 TS t2 Valid Address t13
R/W t15 DATA (wr) t9 ACK t14 t15
Figure 14. Timing Diagram - Non-MUXed Synchronous Write Burst
MPC5121E/MPC5123 Data Sheet, Rev. 1 38
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.7.1.4
Non-MUXed Asynchronous Read Burst Mode (Page Mode)
LPC_CLK t8 CS[x] ADDR[31:n+1] ADDR[n:0] t5 TS t3 OE R/W DATA (rd) t11 ACK t9 t20 t6 t21 t10 t7 t2 Valid Address (Page address) t19 Valid Address Valid Address t4
Figure 15. Timing Diagram - Non-MUXed Asynchronous Read Burst
3.3.7.1.5
Non-MUXed Aynchronous Write Burst Mode
t12 CS[x] t2 Valid Address (Page address) t13
LPC_CLK
ADDR[31:n+1] ADDR[n:0] t5 TS
Valid Address
Valid Address t16
R/W t15 DATA (wr) t9 ACK t14 t15
Figure 16. Timing Diagram - Non-MUXed Aynchronous Write Burst
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
39
Electrical and Thermal Characteristics
3.3.7.2
3.3.7.2.1
MUXed Mode
MUXed non-Burst Mode
LPC_CLK t17 AD[31:0] (wr) Address Valid Write Data t6 AD[31:0] (rd) Address t4 R/W t18 ALE t5 TS t22 CS[x] t3 OE t7
ACK
TSIZ[1:0]
Figure 17. Timing Diagram - MUXed non-Burst Mode
NOTE
ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted.
MPC5121E/MPC5123 Data Sheet, Rev. 1 40
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.7.2.2
MUXed Synchronous Read Burst Mode
LPC_CLK t17 AD[31:0] (rd) Address t18 ALE t5 TS t23 CSx t3 OE t6 t10 t7
R/W t11 ACK t9
Figure 18. Timing Diagram - MUXed Synchronous Read Burst
3.3.7.2.3
MUXed Synchronous Write Burst Mode
LPC_CLK t17 AD[31:0] (wr) Address t18 ALE t5 TS t24 CSx R/W t14 ACK t9 t15 t15 t13
Figure 19. Timing Diagram - MUXed Synchronous Write Burst
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
41
Electrical and Thermal Characteristics
3.3.8
NFC
The NAND flash controller (NFC) implements the interface to standard NAND Flash memory devices. This section describes the timing parameters of the NFC.
NFC_CLE tCLS tCS NFC_CE[1:0] tWP NFC_WE tALS NFC_ALE tDS NFIO[7:0] command tDH tALH tCLH tCH
Figure 20. Command Latch Cycle Timing
NFC_CLE
tCLS tCS tCH
NFC_CE[1:0] tWC tWH tWP NFC_WE tALS NFC_ALE tDS NFIO[7:0] Address tDH tALH
Figure 21. Address Latch Cycle Timing
MPC5121E/MPC5123 Data Sheet, Rev. 1 42
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics NFC_CLE
tCLS tCS
NFC_CE[1:0] tWC tWH tWP NFC_WE
NFC_ALE tDS NFIO[15:0] Data to NF tDH
Figure 22. Write Data Latch Timing
NFC_CLE
NFC_CE[1:0] tRC tREH tRP NFC_RE tAR NFC_ALE tREA tRHZ
NFIO[15:0]
Data from NF tRR
R/B
Figure 23. Read Data Latch Timing Table 24. NFC Timing Characteristics
Timing parameter tCLS tCLH tCS tCH Description NFC_CLE setup Time NFC_CLE Hold Time NFC_CE[1:0] Setup Time NFC_CE[1:0] Hold Time Min. value T+1 T-1 2T-1 T Max. value -- -- -- -- Unit ns ns ns ns SpecID A8.1 A8.2 A8.3 A8.4
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
43
Electrical and Thermal Characteristics
Table 24. NFC Timing Characteristics (continued)
Timing parameter tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH Description NFC_WP Pulse Width NFC_ALE Setup Time NFC_ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time NFC_WE Hold Time Ready to NFC_RE Low NFC_RE Pulse Width READ Cycle Time NFC_RE High Hold Time Min. value T-1 T-1 T-1 T-2 T-1 2T T-1 5T+2 1.5T-1 2T 0.5T Max. value -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns SpecID A8.5 A8.6 A8.7 A8.8 A8.9 A8.10 A8.11 A8.12 A8.13 A8.14 A8.15
T is the flash clock cycle. T= 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz) T= 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
3.3.9
PATA
The MPC5121E/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds). ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5121E/MPC5123 Reference Manual. The MPC5121E/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes. * * Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that required by the ATA-4 specification. Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that required by the ATA-4 specification.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive.
MPC5121E/MPC5123 Data Sheet, Rev. 1 44
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following: * * * The MPC5121E/MPC5123 operating frequency (IP bus clock frequency) Internal MPC5121E/MPC5123 bus latencies Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5121E/MPC5123. See the MPC5121E/MPC5123 Reference Manual.
NOTE
All output timing numbers are specified for nominal 50 pF loads.
3.3.9.1
PATA Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in Table 3-25 specify the ATA timing. Table 3-25. PATA Timing Parameters
Name T ti_ds ti_dh tco PATA Bus clock period Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only) Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only) Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA, ATA_BUFFER_EN Set-up time ATA_DATA to bus clock L-to-H Set-up time ATA_IORDY to bus clock H-to-L Hold time ATA_IORDY to bus clock H to L Max difference in propagation delay bus clock L-to-H to any of following signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN Max difference in buffer propagation delay for any of following signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN Max difference in buffer propagation delay for any of following signals: ATA_IORDY, ATA_DATA (read) Max buffer propagation delay Cable propagation delay for ata_data Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW, ATA_IORDY, ATA_DMACK Meaning Controlled by MPC5121E/M PC5123 MPC5121E/M PC5123 MPC5121E/M PC5123 MPC5121E/M PC5123 MPC5121E/M PC5123 MPC5121E/M PC5123 MPC5121E/M PC5123 MPC5121E/M PC5123 Transceiver Value 15 ns 2 ns 5 ns 2 ns SpecID A9.1 A9.2 A9.3 A9.4
tsu tsui thi tskew1
2 ns 2 ns 2 ns 1.7 ns
A9.5 A9.6 A9.7 A9.8
tskew2
A9.9
tskew3 tbuf tcable1 tcable2
Transceiver Transceiver Cable Cable
A9.10 A9.11 A9.12 A9.13
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
45
Electrical and Thermal Characteristics
Table 3-25. PATA Timing Parameters (continued)
Name tskew4 tskew5 Meaning Max difference in cable propagation delay between: ATA_IORDY and ATA_DATA (read) Max difference in cable propagation delay between: ATA_DIOR, ATA_DIOW, ATA_DMACK and ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DATA (write) Max difference in cable propagation delay without accounting for ground bounce Controlled by Cable Cable Value SpecID A9.14 A9.15
tskew6
Cable
A9.16
3.3.9.2
PIO Mode Timing
t1 ADDR t5 DIOR t6 Read Data (15:0) tA t2r t9
A timing diagram for the PIO read mode is given in Figure 24.
IORDY
IORDY trd1
Figure 24. PIO Read Mode Timing To fulfill read mode timing, the different timing parameters given in Table 3-26 must be observed. Table 3-26. Timing Parameters PIO Read
ATA Parameter t1 t2 t9 PIO Read Mode Timing Parameter t1 t2r t9 Value How to meet SpecID
t1(min) = time_1 * T - (tskew1 + tskew2 + tskew5) t2(min) = time_2r * T - (tskew1 + tskew2 + tskew5) t9(min) = time_9 * T - (tskew1 + tskew2 + tskew6)
calculate and programming time_1, see Reference Manual calculate and programming time_2r, see Reference Manual calculate and programming time_9, see Reference Manual
A9.20 A9.21 A9.22
MPC5121E/MPC5123 Data Sheet, Rev. 1 46
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 3-26. Timing Parameters PIO Read (continued)
ATA Parameter t5 t6 tA PIO Read Mode Timing Parameter t5 t6 tA Value How to meet SpecID
t5(min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 0 tA(min) = (1.5 + time_ax) * T (tco + tsui + tcable2 + tcable2 + 2*tbuf)
If not met, increase time_2r -- calculate and programming time_ax, see Reference Manual
A9.23 A9.24 A9.25
trd
trd1
trd1(max) = (-trd) + (tskew3 + tskew4) calculate and programming trd1(min) = (time_pio_rdx - 0.5 )*T - (tsu + thi) time_pio_rdx, see Reference (time_pio_rdx - 0.5) * T > tsu + thi + tskew3 + tskew4 Manual t0(min) = (time_1 + time_2 + time_9) * T time_1, time_2r, time_9
A9.26
t0
--
A9.27
In PIO write mode, timing waveforms are somewhat different as shown in Figure 25.
t1 ADDR t2r t9
DIOR
DIOW
buffer_en
Write Data (15:0)
ton tA
tB
t4
toff
t1
IORDY
IORDY
Figure 25. PIO Write Mode Timing To fulfill this timing, several parameters need to be observed as shown in Table 3-27.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
47
Electrical and Thermal Characteristics
Table 3-27. Timing Parameters PIO Write
PIO Write ATA Mode Timing Parameter Parameter t1 t2 t1 t2r Value How to meet SpecID
t1(min) = time_1 * T - (tskew1 + tskew2 + tskew5) t2(min) = time_2w * T - (tskew1 + tskew2 + tskew5)
time_1, see Reference Manual calculate and programming time_2w, see Reference Manual time_9, see Reference Manual If not met, increase time_2w calculate and programming time_4, see Reference Manual calculate and programming time_ax, see Reference Manual time_1, time_2r, time_9 -- --
A9.30 A9.31
t9 t3 t4
t9 -- t4
t9(min) = time_9 * T - (tskew1 + tskew2 + tskew6) t3(min) = (time_2w - time_on)* T - (tskew1 + tskew2 +tskew5) t4(min) = time_4 * T - tskew1
A9.32 A9.33 A9.34
tA
tA
tA = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) t0(min) = (time_1 + time_2 + time_9) * T Avoid bus contention when switching buffer on by making ton long enough Avoid bus contention when switching buffer off by making toff long enough
A9.35
t0 -- --
-- -- --
A9.36 A9.37 A9.38
MPC5121E/MPC5123 Data Sheet, Rev. 1 48
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.9.3
Timing in Multiword DMA Mode
Timing in multiword DMA mode is given in Figure 26 and Figure 27.
tk1 DMARQ
ADDR
DMACK
DIOR tm Read Data (15:0) tgr tfr td tk tkjn
Figure 26. MDMA Read Timing
tk1 DMARQ
ADDR
DMACK
buffer_en
DIOW tm Write Data (15:0) ton td1 tk td tkjn toff
Figure 27. MDMA Write Timing To meet this timing, a number of timing parameters must be controlled as shown in Table 3-28.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
49
Electrical and Thermal Characteristics
Table 3-28. Timing Parameters MDMA Read and Write
ATA Parameter MDMA Read/Write Timing Parameter tm
Value
How to meet
SpecID
tm, ti
tm(min) = ti(min) = time_m * T - (tskew1 + tskew2 + tskew5)
calculate and programming time_m, see Reference Manual calculate and programming time_d, see Reference Manual calculate and programming time_k, see Reference Manual time_d, time_k time_d, see Reference Manual -- time_d time_k time_d, time_k calculate and programming time_jn, see Reference Manual --
A9.40
td
td, td1
td1(min) = td(min) = time_d * T - (tskew1 + tskew2 + tskew6)
A9.41
tk
tk
tk(min) = time_k * T - (tskew1 + tskew2 + tskew6)
A9.42
t0 tg(read) tf(read) tg(write) tf(write) tL tn, tj
-- tgr tfr -- -- -- tkjn
t0(min) = (time_d + time_k) * T tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min-drive) = td - te(drive) tfr(min-drive) =0 tg(min-write) = time_d * T -(tskew1 + tskew2 + tskew5) tf(min-write) = time_k * T -(tskew1 + tskew2 + tskew6) tL(max) = (time_d + time_k-2)*T - (tsu + tco + 2*tbuf + 2*tcable2) tn= tj= tkjn = (max(time_k,. time_jn) * T -(tskew1 + tskew2 + tskew6)
A9.43 A9.44 A9.45 A9.46 A9.47 A9.48 A9.49
--
ton toff
ton = time_on * T - tskew1 toff = time_off * T - tskew1
A9.50
3.3.9.4
UDMA In Timing Diagrams
UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in are given: * * * Figure 28 gives timing for UDMA in transfer start Figure 29 gives timing for host terminating UDMA in transfer Figure 30 gives timing for device terminating UDMA in transfer.
MPC5121E/MPC5123 Data Sheet, Rev. 1 50
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics tack ADDR
DMARQ
DMACK tenv DIOR
DIOW tc1 IORDY tc1
Data Read tds tdh
Figure 28. UDMA In Transfer Start Timing Diagram
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
51
Electrical and Thermal Characteristics
ADDR tack DMARQ DMACK DIOR trp DIOW tc1 IORDY Data Read tds Data Write buffer_en tdh tzah tzah ton tdzfs tcvh toff tc1 tx1 tmli tmli
Figure 29. UDMA In Host Terminates Transfer
ADDR tack DMARQ DMACK DIOR DIOW tmli tc1 IORDY Data Read tds Data Write buffer_en tdh tzah tzah ton tdzfs tcvh toff tmli tc1 tss1 tli5
Figure 30. UDMA In Device Terminates Transfer Timing parameters are explained in Table 29.
MPC5121E/MPC5123 Data Sheet, Rev. 1 52
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 29. Timing Parameters UDMA in Burst
ATA Parameter tack UDMA In Timing Parameter tack Value How to Meet SpecID
tack(min) = (time_ack * T) - (tskew1 + tskew2 )
calculate and programming time_ack, see Reference Manual calculate and programming time_env, see Reference Manual tskew3, ti_ds, ti_dh should be low enough Bus clock period T big enough calculate and programming time_rp, see Reference Manual
A9.51
tenv
tenv
tenv(min) = (time_env * T) - (tskew1 + tskew2) tenv(max) = (time_env * T) + (tskew1 + tskew2) tds - (tskew3) - ti_ds > 0 tdh - (tskew3) -ti_dh > 0 (tcyc - tskew ) > T trp(min) = time_rp * T - (tskew1 + tskew2 + tskew6)
A9.52
tds tdh tcyc trp
tds1 tdh1 tc1 trp
A9.53 A9.54 A9.55 A9.56
tx11 -- tmli tmli1
(time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs calculate and (drive) programming time_rp, see Reference Manual tmli1(min) = (time_mlix + 0.4) * T calculate and programming time_mlix, see Reference Manual calculate and programming time_zah, see Reference Manual calculate and programming time_dzfs, see Reference Manual calculate and programming time_cvh, see Reference Manual --
A9.57
A9.58
tzah
tzah
tzah(min) = (time_zah + 0.4) * T
A9.59
tdzfs
tdzfs
tdzfs = (time_dzfs * T) - (tskew1 + tskew2)
A9.60
tcvh
tcvh
tcvh = (time_cvh *T) - (tskew1 + tskew2)
A9.61
--
1
ton toff2
ton = time_on * T - tskew1 toff = time_off * T - tskew1
A9.62
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2 Make TON and TOFF big enough to avoid bus contention.
3.3.9.5
UDMA Out Timing Diagrams
UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA out are given: * * * Figure 31 gives timing for UDMA out transfer start Figure 32 gives timing for host terminating UDMA out transfer Figure 33 gives timing for device terminating UDMA out transfer.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
53
Electrical and Thermal Characteristics tack ADDR DMARQ
DMACK tenv DIOW
DIOR tcyc buffer_en ton Data Write tli1 IORDY trfs1 tdzfs tdvs tdvh tdvs tcyc
Figure 31. UDMA Out Transfer Start Timing Diagram
ADDR tack DMARQ
DMACK tss DIOW
DIOR tcyc tli2 tcyc1 Data Write tdzfs_mli tcvh toff
IORDY tli3 buffer_en
Figure 32. UDMA Out Host Terminates Transfer
MPC5121E/MPC5123 Data Sheet, Rev. 1 54
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
r
ADDR tack DMARQ tli2 DMACK DIOW
DIOR trfs1 Data Write tcyc tdzfs_mli tcvh toff
IORDY
buffer_en
Figure 33. UDMA Out Device Terminates Transfer Timing parameters are explained in Table 30. Table 30. Timing Parameters UDMA Out Burst
ATA Parameter tack UDMA Out Timing Parameter tack Value tack(min) = (time_ack * T) - (tskew1 + tskew2) How to meet calculate and programming time_ack, see Reference Manual calculate and programming time_env, see Reference Manual calculate and programming time_dvs, see Reference Manual calculate and programming time_dvh, see Reference Manual calculate and programming time_cyc, see Reference Manual SpecID A9.63
tenv
tenv
tenv(min) = (time_env * T) - (tskew1 + tskew2) tenv(max) = (time_env * T) + (tskew1 + tskew2)
A9.64
tdvs
tdvs
tdvs = (time_dvs * T) - (tskew1 + tskew2)
A9.65
tdvh
tdvh
tdvs = (time_dvh * T) - (tskew1 + tskew2)
A9.66
tcyc
tcyc
tcyc = time_cyc * T - (tskew1 + tskew2)
A9.67
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
55
Electrical and Thermal Characteristics
Table 30. Timing Parameters UDMA Out Burst (continued)
ATA Parameter t2cyc -- UDMA Out Timing Parameter Value t2cyc = time_cyc * 2 * T How to meet calculate and programming time_cyc, see Reference Manual -- calculate and programming time_dzfs, see Reference Manual calculate and programming time_ss, see Reference Manual -- -- -- -- calculate and programming time_cvh, see Reference Manual -- SpecID A9.68
trfs1
trfs tdzfs
trfs = 1.6 * T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs * T - (tskew1)
A9.69 A9.70
--
tss
tss
tss = time_ss * T - (tskew1 + tskew2)
A9.71
tmli tli tli tli tcvh
tdzfs_mli tli1 tli2 tli3 tcvh
tdzfs_mli =max(time_dzfs, time_mli) * T - (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh *T) - (tskew1 + tskew2)
A9.72 A9.73 A9.74 A9.75 A9.76
--
ton toff
ton = time_on * T - tskew1 toff = time_off * T - tskew1
A9.77
3.3.10
SATA PHY
1.5 Gbps SATA PHY Layer See "Serial ATA: High Speed Serialized AT Attachment" Revision 1.0a, 7-January-2003.
3.3.11
*
FEC
AC Test Timing Conditions: Output Loading All Outputs: 25 pF Table 31. MII Rx Signal Timing
Sym t1 t2 t3 t4 Description RXD[3:0], RX_DV, RX_ER to RX_CLK setup RX_CLK to RXD[3:0], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns RX_CLK Period1 RX_CLK Period
1
SpecID A11.1 A11.2 A11.3 A11.4
MPC5121E/MPC5123 Data Sheet, Rev. 1 56
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
1
RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification. t3 RX_CLK (Input) t4
RXD[3:0] (inputs) RX_DV RX_ER t1 t2
Figure 34. Ethernet Timing Diagram - MII Rx Signal Table 32. MII Tx Signal Timing
Sym t5 t6 t7 t8
1
Description TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER invalid TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low
Min 3 -- 35% 35%
Max -- 25 65% 65%
Unit ns ns TX_CLK TX_CLK Period1 Period1
SpecID A11.5 A11.6 A11.7 A11.8
The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification. t7 TX_CLK (Input) t5 TXD[3:0] (Outputs) TX_EN TX_ER t6 t8
Figure 35. Ethernet Timing Diagra - MII Tx Signal Table 33. MII Async Signal Timing
Sym t9 Description CRS, COL minimum pulse width Min 1.5 Max -- Unit TX_CLK Period SpecID A11.9
CRS, COL t9
Figure 36. Ethernet Timing Diagram - MII Async
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
57
Electrical and Thermal Characteristics
Table 34. MII Serial Management Channel Signal Timing
Sym t10 t11 t12 t13 t14 t15
1
Description MDC falling edge to MDIO output delay MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high
1
Min 0 10 0 160 160 400
Max 25 -- -- -- -- --
Unit ns ns ns ns ns ns
SpecID A11.10 A11.11 A11.12 A11.13 A11.14 A11.15
MDC pulse width low1 MDC period2
MDC is generated by MPC5121E/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5121E/MPC5123 Reference Manual. 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5121E/MPC5123 Reference Manual. t13 t14 MDC (Output) t15 t10 MDIO (Output)
MDIO (Input)
t11
t12
Figure 37. Ethernet Timing Diagram - MII Serial Management
3.3.12
USB ULPI
This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004.
MPC5121E/MPC5123 Data Sheet, Rev. 1 58
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Clock TSC Control In (dir, nxt) TSD Data In (8-bit) THD THC
TDC Control Out (stp) TDD Data Out (8-bit)
TDC
Figure 38. ULPI Timing Diagram Table 35. Timing Specifications - ULPI
Sym TCK Clock Period Description Min 15 -- 0.0 -- Max -- 6.0 9.0 Units ns ns ns ns SpecID A12.1 A12.2 A12.3 A12.4
TSC, TSD Setup time (control in, 8-bit data in) THC, THD Hold time (control in, 8-bit data in) TDC, TDD Output delay (control out, 8-bit data out)
NOTE
Output timing is specified at a nominal 50 pF load.
3.3.13
On-Chip USB PHY
The USB PHY is an USB2.0 compatible PHY integrated on-chip. See Chapter 7 in the USB Specification Rev. 2.0 at www.usb.org.
3.3.14
SDHC
Figure 39 depicts the timings of the SDHC.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
59
Electrical and Thermal Characteristics
SD4 SD2 SD5 MMCx_CLK SD3 Output from SDHC to card MMCx_CMD MMCx_DAT_0 MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 MMCx_CMD MMCx_DAT_0 MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD6 SD7 SD1
SD8
Input from card to SDHC
Figure 39. SDHC Timing Diagram Table 36 lists the timing parameters.
.
Table 36. MMC/SD Interface Timing Parameters
ID Parameter Symbols Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time (Full Speed/High Speed) Clock High Time (Full Speed/High Speed) Clock Rise Time (Full Speed/High Speed) Clock Fall Time (Full Speed/High Speed) fPP1 fPP2 fPP3 fOD4 tWL tWH tTLH tTHL 0 0 0 100 10/7 10/7 10/3 10/3 400 25/50 20/52 400 kHz MHz MHz kHz ns ns ns ns A14.1 A14.2 A14.3 A14.4 A14.5 A14.6 A14.7 A14.8 Min Max Unit SpecID
SDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SD7 SDHC Output for Card Input Setup SDHC Output for Card Input Hold tOSU tOH 15 15 ns ns A14.9 A14.10
SDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD8
1 2
SDHC Input Setup Time
tISU
8
ns
A14.11
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. 4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.
MPC5121E/MPC5123 Data Sheet, Rev. 1 60
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.15
DIU
The DIU is a display controller designed to manage the TFT LCD display.
3.3.15.1
Interface to TFT LCD Panels, Functional Description
Figure 40 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: * * * * DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DIU_CLK runs continuously. This signal frequency could be from 5 to 100 MHz depending on the panel type. DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse. DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse. DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
DIU_VSYNC DIU_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
DIU_HSYNC DIU_DE 1 DIU_CLK DIU_LD[23:0] 2 3 m-1 m
Figure 40. Interface Timing Diagram for TFT LCD Panels
3.3.15.2
Interface to TFT LCD Panels, Electrical Characteristics
Figure 41 depicts the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal (meaning the data and sync. signals change at the rising edge of it) and active-high polarity of the DIU_HSYNC, DIU_VSYNC and DIU_DE signal. You can select the polarity of the DIU_HSYNC and DIU_VSYNC signal via the SYN_POL register, whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. And, pixel clock inversion and a flexible programmable pixel clock delay is also supported, programed via the DIU Clock Config Register (DCCR) in the system clock module.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
61
Electrical and Thermal Characteristics tHSP Start of line tPWH tPCP DIU_CLK tBPH tSW tFPH
DIU_LD[23:0]
Invalid Data
1 1
2
3
DELTA_X Invalid Data
DIU_HSYNC
DIU_DE
Figure 41. TFT LCD Interface Timing Diagram - Horizontal Sync Pulse Figure 42 depicts the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown in the diagram are programmable.
tVSP Start of Frame tPWV tHSP tBPV tSH tFPV
DIU_HSYNC
DIU_LD[23:0] (Line Data)
Invalid Data
1
2
3
DELTA_Y
Invalid Data
DIU_VSYNC
DIU_DE
Figure 42. TFT LCD Interface Timing Diagram - Vertical Sync Pulse Table 39 shows timing parameters of signals. Table 37. LCD Interface Timing Parameters - Pixel Level
Name tPCP tPWH tBPH Description Display Pixel Clock Period HSYNC Pulse Width HSYNC Back Porch Width 151 PW_H * tPCP BP_H * tPCP Value Unit ns ns ns SpecID A15.1 A15.2 A15.3
MPC5121E/MPC5123 Data Sheet, Rev. 1 62
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 37. LCD Interface Timing Parameters - Pixel Level (continued)
Name tFPH tSW tHSP tPWV tBPV tFPV tSH tVSP
1
Description HSYNC Front Porch Width Screen Width HSYNC (Line) Period VSYNC Pulse Width VSYNC Back Porch Width VSYNC Front Porch Width Screen Height VSYNC (Frame) Period FP_H * tPCP DELTA_X * tPCP
Value
Unit ns ns ns ns ns ns ns ns
SpecID A15.4 A15.5 A15.6 A15.7 A15.8 A15.9 A15.10 A15.11
(PW_H + BP_H + DELTA_X + FP_H) * tPCP PW_V * tHSP BP_V * tHSP FP_V * tHSP DELTA_Y * tHSP (PW_V + BP_V + DELTA_Y + FP_H) * tHSP
Display interface pixel clock period immediate value (in nanosecond).
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; And the PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions on these parameters. Figure 38 depicts the synchronous display interface timing for access level, and Table 39 lists the timing parameters.
tCHD DIU_HSYNC DIU_VSYNC DIU_DE tCSU
DIU_CLK tCKH tCKL tDHD tDSU
DIU_LD[23:0]
Figure 43. LCD Interface Timing Diagram - Access Level Table 38. LCD Interface Timing Parameters - Access Level
Parameter tCKH tCKL tDSU tDHD tCSU tCHD Description LCD Interface Pixel Clock High Time LCD Interface Pixel Clock Low Time LCD Interface Data Setup Time LCD Interface Data Hold Time LCD Interface Control Signal Setup Time LCD Interface Control Signal Hold Time Min tPCP * 0.4 tPCP * 0.4 5.0 6.0 5.0 6.0 Typ tPCP * 0.5 tPCP * 0.5 Max tPCP * 0.6 tPCP * 0.6 Unit ns ns ns ns ns ns SpecID A15.12 A15.13 A15.14 A15.15 A15.16 A15.17
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
63
Electrical and Thermal Characteristics
3.3.16
SPDIF
The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the clock.
3.3.17
CAN
The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT_RTC domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
3.3.18
I2C
Table 39. I2C Input Timing Specifications - SCL and SDA
This section specifies the timing parameters of the Inter-Integrated Circuit (I2C) interface. Refere to the I2C-Bus Specification.
Sym 1 2 4 6 7 8 9
1
Description Start condition hold time Clock low time Data hold time Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 2 8 0.0 4 0.0 2 2
Max -- -- -- -- -- -- --
Units IP-Bus Cycle1 IP-Bus Cycle ns IP-Bus Cycle1 ns IP-Bus Cycle
1 1
SpecID A18.1 A18.2 A18.3 A18.4 A18.5 A18.6 A18.7
IP-Bus Cycle1
Inter Peripheral Clock is defined in the MPC5121E/MPC5123 Reference Manual.
Table 40. I2C Output Timing Specifications - SCL and SDA
Sym 11 21 33 4
1
Description Start condition hold time Clock low time SCL/SDA rise time Data hold time SCL/SDA fall time Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 10 -- 7 -- 10 2 20 10
Max -- -- 7.9 -- 7.9 -- -- -- --
Units IP-Bus Cycle2 IP-Bus Cycle2
SpecID A18.8 A18.9 A18.10
2
ns IP-Bus Cycle ns IP-Bus Cycle2
A18.11 A18.12 A18.13 A18.14 A18.15 A18.16
51 6
1
71 81 91
1
IP-Bus Cycle2 IP-Bus Cycle2
IP-Bus Cycle2 I2C
Programming IFDR with the maximum frequency results in the minimum output timings listed. The interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values
MPC5121E/MPC5123 Data Sheet, Rev. 1 64
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3
Inter Peripheral Clock is defined in the MPC5121E/MPC5123 Reference Manual
NOTE
Output timing is specified at a nominal 50 pF load.
2 SCL 3 6 5
1
4
7
8
9
SDA
Figure 44. Timing Diagram - I2C Input/Output
3.3.19
J1850
See the MPC5121E/MPC5123 Reference Manual.
3.3.20
PSC
The Programmable Serial Controllers (PSC) support different modes of operation (Codec, AC97, SPI).
3.3.20.1
Codec Mode (8,16,24 and 32-bit)/I2S Mode
Table 41. Timing Specifications - 8,16, 24, and 32-bit CODEC/I2S Master Mode
Sym 1 2 3 4 5 6 7 8
1
Description Bit Clock cycle time, programmed in CCS register Clock duty cycle Bit Clock fall time Bit Clock rise time FrameSync valid after clock edge FrameSync invalid after clock edge Output Data valid after clock edge Input Data setup time
Min 40.0 45 -- -- -- -- -- 6.0
Typ -- 50 -- -- -- -- -- --
Max -- 55 7.9 7.9 8.4 8.4 9.3 --
Units ns %1 ns ns ns ns ns ns
SpecID A20.1 A20.2 A20.3 A20.4 A20.5 A20.6 A20.7 A20.8
Bit Clock cycle time
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
65
Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Output BitClk (CLKPOL=1) Output 5 FrameSync (SyncPol = 1) Output FrameSync (SyncPol = 0) Output 7 TxD Output 8 RxD Input
3 2 2 4
4 3
6
Figure 45. Timing Diagram - 8,16, 24, and 32-bit CODEC/I2S Master Mode Table 42. Timing Specifications - 8,16, 24, and 32-bit CODEC/I2S Slave Mode
Sym 1 2 3 4 5 6
1
Description Bit Clock cycle time Clock duty cycle FrameSync setup time Output Data valid after clock edge Input Data setup time Input Data hold time
Min 40.0 -- 1.0 -- 1.0 1.0
Typ -- 50 -- -- -- --
Max -- -- -- 14.0 -- --
Units ns %1 ns ns ns ns
SpecID A20.9 A20.10 A20.11 A20.12 A20.13 A20.14
Bit Clock cycle time
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 66
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics 1
BitClk (CLKPOL=0) Input BitClk (CLKPOL=1) Input
2
2
3 FrameSync (SyncPol = 1) Input FrameSync (SyncPol = 0) Input 4 TxD Output 5 RxD Input 6
Figure 46. Timing Diagram - 8,16, 24, and 32-bit CODEC/I2S Slave Mode
3.3.20.2
AC97 Mode
Table 43. Timing Specifications - AC97 Mode
Sym 1 2 3 4 5 6 7 Bit Clock cycle time
Description
Min -- -- -- -- -- 1.0 1.0
Typ 81.4 40.7 40.7 -- -- -- --
Max -- -- -- 13.0 14.0 -- --
Units ns ns ns ns ns ns ns
SpecID A20.15 A20.16 A20.17 A20.18 A20.19 A20.20 A20.21
Clock pulse high time Clock pulse low time FrameSync valid after rising clock edge Output Data valid after rising clock edge Input Data setup time Input Data hold time
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
67
Electrical and Thermal Characteristics 1
BitClk (CLKPOL=0) Input FrameSync (SyncPol = 1) Output Sdata_out Output
3 4
2
5
6 Sdata_in Input
7
Figure 47. Timing Diagram - AC97 Mode
3.3.20.3
SPI Mode
Table 44. Timing Specifications - SPI Master Mode, Format 0 (CPHA = 0)
Sym 1 2 3 4 5 6 7 8 9 10 11
Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time
Min 30.0 15.0 30.0 -- -- 6.0 1.0 -- 15.0 -- --
Max -- -- -- 8.9 8.9 -- -- TSCK -- 7.9 7.9
Units ns ns ns ns ns ns ns ns ns ns ns
SpecID A20.26 A20.27 A20.28 A20.29 A20.30 A20.31 A20.32 A20.33 A20.34 A20.35 A20.36
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 68
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics 1 10 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output
11
2
2 11
10
8
9
4 MOSI Output 6 MISO Input
5
6
7
7
Figure 48. Timing Diagram - SPI Master Mode, Format 0 (CPHA = 0) Table 45. Timing Specifications - SPI Slave Mode, Format 0 (CPHA = 0)
Sym 1 2 3 4 5 6 7 8 9 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Input Data setup time Input Data hold time Output data valid after SS Output data valid after SCK Slave disable lag time Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time Min 30.0 15.0 1.0 1.0 1.0 -- -- 0.0 30.0 Max -- -- -- -- -- 14.0 14.0 -- -- Units ns ns ns ns ns ns ns ns -- SpecID A20.37 A20.38 A20.39 A20.40 A20.41 A20.42 A20.43 A20.44 A20.45
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
69
Electrical and Thermal Characteristics 1
SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input
2
2
8
9
4 MOSI Input 6 MISO Output 7
5
Figure 49. Timing Diagram - SPI Slave Mode, Format 0 (CPHA = 0) Table 46. Timing Specifications - SPI Master Mode, Format 1 (CPHA = 1)
Sym 1 2 3 4 5 6 7 8 9 10 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 -- 6.0 1.0 -- 15.0 -- -- Max -- -- -- 8.9 -- -- TSCK -- 7.9 7.9 Units ns ns ns ns ns ns ns ns ns ns SpecID A20.46 A20.47 A20.48 A20.49 A20.50 A20.51 A20.52 A20.53 A20.54 A20.55
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 70
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output
10
2
2 10
9
7
8
4 MOSI Output 5 MISO Input 6
Figure 50. Timing Diagram - SPI Master Mode, Format 1 (CPHA = 1) Table 47. Timing Specifications - SPI Slave Mode, Format 1 (CPHA = 1)
Sym 1 2 3 4 5 6 7 8 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time Min 30.0 15.0 0.0 -- 2.0 1.0 0.0 30.0 Max -- -- -- 14.0 -- -- -- -- Units ns ns ns ns ns ns ns ns SpecID A20.56 A20.57 A20.58 A20.59 A20.60 A20.61 A20.62 A20.63
NOTE
Output timing is specified at a nominal 50 pF load.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
71
Electrical and Thermal Characteristics 1
SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input
2
2
7
8
5 MOSI Input 4 MISO Output
6
Figure 51. Timing Diagram - SPI Slave Mode, Format 1 (CPHA = 1)
3.3.21
GPIOs and Timers
The MPC5121E/MPC5123 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The external events (GPIO or timer inputs) are asynchronous to the system clock. The inputs must be valid for at least tIOWID to ensure proper capture by the internal IP clock. Table 48. GPIO/Timers Input AC Timing Specifications
Symbol tIOWID
1
Description GPIO/Timers inputs - minimum pulse witdh
Min 2T1
Unit ns
SpecID A21.1
T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus freqency of 83 MHz).
3.3.22
Fusebox
Table 49. Fusebox Characteristics
Table 49 gives the Fusebox specification.
Sym tFUSEWR Program
1
Description time1 for Fuse
Min 125 --
Max -- 10
Units us mA
SpecID A22.1 A22.2
IFUSEWR Program current to program one fuse bit
The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module.
MPC5121E/MPC5123 Data Sheet, Rev. 1 72
Preliminary
Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.23
Sym -- 1 2 3 4 5 6 7 8 9 10 11 12 13
1 2
IEEE 1149.1 (JTAG)
Table 50. JTAG Timing Specification
Characteristic TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.5V TCK rise and fall times TRST setup time to tck falling edge TRST assert time Input data setup time Input data hold time2 TCK to output data valid
3 3 2 1
Min 0 40 1.08 0 10 5 5 15 0 0 5 1 0 0
Max 25 -- -- 3 -- -- -- -- 30 30 -- -- 15 15
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
SpecID A23.1 A23.2 A23.3 A23.4 A23.5 A23.6 A23.7 A23.8 A23.9 A23.10 A23.11 A23.12 A23.13 A23.14
TCK to output high impedance TMS, TDI data setup time. TMS, TDI data hold time. TCK to TDO data valid. TCK to TDO high impedance.
TRST is an asynchronous signal. The setup time is for test purposes only. Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. 1 2 2
TCK
VM
VM
VM
3
3
VM = Midpoint Voltage Numbers shown reference JTAG Timing Specification Table
Figure 52. Timing Diagram - JTAG Clock Input
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
73
Electrical and Thermal Characteristics
TCK 4 TRST 5
Numbers shown reference JTAG Timing Specification Table
Figure 53. Timing Diagram - JTAG TRST
TCK 6 Data Inputs 8 Output Data Valid 9 Data Outputs
Numbers shown reference JTAG Timing Specification Table
7
Input Data Valid
Data Outputs
Figure 54. Timing Diagram - JTAG Boundary Scan
TCK 10 TDI, TMS 12 Output Data Valid 13 TDO
Numbers shown reference JTAG Timing Specification Table
11
Input Data Valid
TDO
Figure 55. Timing Diagram - Test Access Port
MPC5121E/MPC5123 Data Sheet, Rev. 1 74
Preliminary
Freescale Semiconductor
System Design Information
3.3.24
VIU
The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream. Figure 56 shows the VIU interface timing and Table 51 lists the timing parameters.
VIU_PIX_CLK fPIX_CLK tDHD tDSU
VIU_DATA[9:0]
Figure 56. VIU Interface Timing Diagram Table 51. VIU Interface Timing Parameters
Parameter fPIX_CK tDSU tDHD Description VIU Pixel Clock Frequency VIU Data Setup Time VIU Data Hold Time Min 2.5 2.5 Typ Max 83 Unit MHz ns ns SpecID A24.1 A24.2 A24.3
4
4.1
System Design Information
Power Up/Down Sequencing
Power sequencing between the 1.4 V power supply VDD_CORE and the remaing supplies is required to prevent excessive current during power up phase. The recommended power sequence is as follows: * * Use 12V/millisecond or slower time for all supplies. Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, AVDD_FUSERD, USB PHY & SATA PHY supplies first in any order and then power up VDD_CORE. If required AVDD_FUSEWR should be powered up afterwards. All the supplies must reach the specified operating conditions before the PORESET can be released. For power down, drop AVDD_FUSEWR to 0V first, drop VDD_CORE to 0V, and then drop all other supplies. VDD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC or PLL_AVDDs by more than 0.4 V at any time, including power-up.
* * *
4.2
System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 57 is a recommendation for the required filter circuit. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. All traces should be as low impedance as possible, especially ground pins to the ground plane.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
75
System Design Information
The filter for System/Core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the planes. In addition to keeping the filter components for System/Core PLLVDD as close as practical to the body of the MPC5121E as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the MPC5121E. The capacitors for C2 in the figure below should be rated X5R or better due to temperature performance.
R1=10 Power supply source C1=1 F C2=0.1 F AVDD device pin
Figure 57. Power Supply Filtering
4.3
Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD and VSS pins of the MPC5121E/MPC5123. The unused AVDD_FUSEWR power should be connecetd to VSS directly or via a resistor. For DDR or LPDDR modes the unused pins VTT[3:0] for DDR2 Termination voltage can be unconnected. The SATA PHY needs to be powered even if it is not used in an application. In this case, you should not enable the SATA oscillator and the SATA PHY by software.
MPC5121E/MPC5123 VSS NC NC NC NC NC NC NC VDD_IO VDD_CORE 1.7-2.6V VDD_CORE VSS VSS VSS SATA_XTALI SATA_XTALO SATA_ANAVIZ SATA_RESREF SATA_TXP SATA_TXN SATA_RXP SATA_RXN SATA_VDDA_3P3 SATA_VDDA_1P2 SATA_VDDA_VREG SATA_PLL_VDDA1P2 SATA_PLL_VSSA SATA_RX_VSSA SATA_TX_VSSA
Figure 58. Recommended Connection for Pins of Unused SATA PHY
MPC5121E/MPC5123 Data Sheet, Rev. 1 76
Preliminary
Freescale Semiconductor
System Design Information MPC5121E/MPC5123 VSS NC NC USB_XTALI USB_XTALO USB_TPA USB_DP USB_DN USB_VBUS USB_UID USB_PLL_GND USB_PLL_PWR3 USB_RREF USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA
Weak pull-up or pull-down VDD_IO VSS VSS VSS VSS VSS VSS VSS VDD_IO
Figure 59. Recommended connection for pins of unused USB PHY
4.4
Pull-Up/Pull-Down Resistor Requirements
The MPC5121E/MPC5123 requires external pull-up or pull-down resistors on certain pins.
4.4.1
Pull-Down Resistor Requirements for TEST pin
The MPC5121E/MPC5123 requires a pull-down resistor on the test pin TEST.
4.4.2
Pull-Up Requirements for the PCI Control Lines
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ. Refer to the PCI Local Bus specification.
4.5
JTAG
The MPC5121E/MPC5123 provides you with an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5121E/MPC5123's embedded e300 processor and to other on-chip resources. This interface provides a means for executing test routines and for performing software development and debug functions.
4.5.1
TRST
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset performance, the TRST signal must be asserted during power-on reset.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
77
System Design Information
4.5.1.1
TRST and PORESET
The JTAG interface can control the direction of the MPC5121E/MPC5123 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5121E/MPC5123 comes out of power-on reset; do this by asserting TRST before PORESET is released. For more details refer to the Reset and JTAG Timing Specification.
PORESET Required assertion of TRST Optional assertion of TRST
TRST
Figure 60. PORESET vs. TRST
4.5.2
e300 COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
4.5.2.1
Boards Interfacing the JTAG Port via a COP Connector
The MPC5121E/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP/BDM interface. Table 52 gives the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order. Table 52. COP/BDM Interface Signals
BDM Pin # 16 15 14 13 12 11 10 9 8 7 6 5 4 3 MPC5121E/MPC51 BDM Connector 23 I/O Pin -- CKSTP_OUT -- HRESET -- SRESET -- TMS CKSTP_IN TCK -- See Note3 TRST TDI GND ckstp_out KEY hreset GND sreset N/C tms ckstp_in tck VDD 2 halted3 trst tdi Internal Pull Up/Down -- -- -- Pull-Up -- Pull-Up -- Pull-Up -- Pull-Up -- -- Pull-Up Pull-Up External Pull Up/Down -- 10k Pull-Up -- 10k Pull-Up -- 10k Pull-Up -- 10k Pull-Up 10k Pull-Up 10k Pull-Up -- -- 10k Pull-Up 10k Pull-Up I/O 1 -- I -- O -- O -- O O O -- I O O
MPC5121E/MPC5123 Data Sheet, Rev. 1 78
Preliminary
Freescale Semiconductor
System Design Information
Table 52. COP/BDM Interface Signals (continued)
BDM Pin # 2 1
1
MPC5121E/MPC51 BDM Connector 23 I/O Pin See Note4 TDO qack4 tdo
Internal Pull Up/Down -- --
External Pull Up/Down -- --
I/O 1 O I
With respect to the emulator tool's perspective: Input is really an output from the embedded e300 core. Output is really an input to the core. 2 From the board under test, power sense for chip power. 3 HALTED is not available from e300 core. 4 Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5121E/MPC5123 internally ties CORE_QACK to GND in its normal/functional mode (always asserted).
For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG module, only wiring TRST and PORESET is not recommended. To reset the MPC5121E/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5121E/MPC5123. The circuitry shown in Figure 61 allows the COP to assert HRESET or TRST separately, while any other board sources can drive PORESET.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
79
System Design Information
PORESET COP Header 13 11 16 COP Connector Physical Pinout 1 3 5 7 9 11 13 15 2 4 6 8 7 10 12 K 16 15 62 1 3 HRESET SRESET 10Kohm 10Kohm TRST 10Kohm
PORESET HRESET VDD_IO VDD_IO SRESET VDD_IO 4 14 9 12 TCK VDD_IO TDO TDI 10Kohm VDD_IO TDI CKSTP_OUT 10Kohm VDD_IO CKSTP_OUT 8 5 (3) 2 (4) 10 CKSTP_IN halted qack 10Kohm VDD_IO CKSTP_IN (LPC_CLK) NC NC NC 10Kohm VDD_IO TCK TDO TMS 10Kohm VDD_IO TMS
TRST
Figure 61. COP Connector Diagram
4.5.2.2
Boards Without COP Connector
If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal (PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 62 shows the connection of the JTAG interface without COP connector.
MPC5121E/MPC5123 Data Sheet, Rev. 1 80
Preliminary
Freescale Semiconductor
Package Information
PORESET HRESET SRESET 10 Kohm 10 Kohm
PORESET HRESET VDD_IO VDD_IO SRESET
TRST 10 Kohm VDD_IO JTAG_TMS 10 Kohm VDD_IO TCK 10 Kohm VDD_IO TDI CKSTP_OUT TDO
Figure 62. TRST Wiring for Boards without COP Connector
5
Package Information
This section details package parameters and dimensions. The MPC5121E/MPC5123 is available in a Thermally Enhanced Plastic Ball Grid Array (TEPBGA), see Section 5.1, "Package Parameters," and Section 5.2, "Mechanical Dimensions," for information on the TEPBGA.
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
81
Package Information
5.1
Package Parameters
Table 53. TEPBGA Paramaters
Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) 27 mm x 27 mm 516 1.00 mm 2.25 mm 96.5 Sn/3.5Ag (VY package) 0.6 mm
5.2
Mechanical Dimensions
MPC5121E/MPC5123 Data Sheet, Rev. 1 82
Preliminary
Freescale Semiconductor
Package Information
1 2 3 4 SATA_ RXN 5 SATA_ RXP 6 7 8 9 10 11 12 13 14 15 16 17 18 CAN1 _TX 19 20 21 22 USB_ DM 23 USB_ DP 24 USB_ TPA 25 26
A
VSS
VSS
SATA_ PSC7_ PSC7_ PSC6_ PSC6_ PSC6_ PSC11 PSC10 PSC2_ PSC1_ PSC1_ PSC0_ RX_V 4 3 4 2 0 _0 _2 3 3 1 1 SSA
USB2_ GPIO2 XTALO DRVV 8 _RTC BUS USB2_ VBUS _PWR _FAUL T USB_ VDDA
VSS
B
VSS
VSS
VSS
SATA_ RX_V SSA
VSS
PSC8_ 3
VSS
PSC7_ PSC6_ VDD_I PSC11 0 3 O _1
VSS
PSC10 PSC2_ VDD_I PSC0_ _1 1 O 4
VSS
GPIO3 1
CAN2 _RX
VSS
VSS
USB_ VSSA _BIAS
USB_ VDD_I XTALO O
VSS
C
VSS
SATA_ SATA_ XTALO XTALI
VSS
SATA_ PSC9_ PSC8_ PSC7_ VDDA 0 2 2 _1P2 SATA_ VDDA PSC9_ PSC9_ PSC8_ _VRE 3 1 1 G
AVDD _FUS EWR AVDD _FUS ERD
PSC6_ PSC11 PSC10 PSC10 PSC2_ PSC1_ PSC0_ 1 _2 _3 _0 0 0 3
PSC_ MCLK _IN
GPIO3 0
CAN1 _RX
XTALI _RTC
USB_ VSSA
VSS
USB_ XTALI
VSS
PCI_C LK
D
SATA_ VDDA _1P2
VSS
SATA_ PLL_V SSA SATA_ PLL_V DDA1 P2 VSS
SATA_ VDDA _3P3
VDD_I PSC11 O _4
VSS
PSC2_ PSC1_ VDD_I PSC0_ 4 4 O 0
VSS
HIB_M VBAT_ ODE RTC
USB_ VDDA
USB_ VBUS
USB_ VDDA _BIAS
USB_ PLL_P WR3
VSS
VSS
PCI_R EQ2
E
SATA_ TXN
SATA_ VDDA _1P2
SATA_ RESR EF
SATA_ PSC9_ PSC9_ PSC8_ PSC8_ PSC7_ PSC11 PSC10 PSC2_ PSC1_ PSC0_ ANAVI 4 2 4 0 1 _3 _4 2 2 2 Z VDD_I O VDD_I O VDD_I O
CAN2 _TX
GPIO2 9
VSS
USB_ UID
USB_ VSSA
USB_ VSSA
USB_ RREF
USB_ PCI_G PCI_G PLL_G NT2 NT0 ND VDD_I O PCI_R EQ0 PCI_A D30 PCI_A D29 PCI_A D24 PCI_A D23 VDD_I O PCI_A D26
PCI_R EQ1
F
SATA_ TXP SATA_ TX_VS SA NFC_ RB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_I O
VSS
PCI_R ST PCI_G NT1
PCI_A D28 PCI_C BE3 PCI_A D21 PCI_A D18
G
NFC_ RE PATA_ DACK
NFC_ WE NFC_ CE0
NFC_ WP NFC_ ALE PATA_ DRQ
VSS
H
NFC_ CLE VDD_I O
VSS
VDD_I O
PCI_A D31 PCI_A D27
VSS
VSS
J
PATA_I PATA_I PATA_I OCHR OR NTRQ DY PATA_ CE1
PCI_A D25
PCI_A D20
K
PATA_I VDD_I VDD_I PATA_I SOLAT OW O O E EMB_ AD02 EMB_ AD01 EMB_ AD05 EMB_ AD08 EMB_ AD11 EMB_ AD16 EMB_ AD20 EMB_ AD00 PATA_ CE2 EMB_ AD04 VSS EMB_ AD12 EMB_ AD19 EMB_ AD23
VSS
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VSS
PCI_I DSEL
PCI_A D22
PCI_A D19
PCI_A D17
PCI_I RDY PCI_D EVSE L PCI_S ERR PCI_A D15 PCI_A D12 PCI_A D08 PCI_A D07
L
EMB_ AD03 EMB_ AD06 EMB_ AD10 EMB_ AD15 EMB_ AD17 EMB_ AD22
VSS
VDD_ CORE VDD_ CORE
VSS
VSS
VSS
VSS
VSS
VSS
VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE
VSS
PCI_A D16 PCI_T RDY
VDD_I O PCI_F RAME VSS PCI_A D09 PCI_A D06 VDD_I O
PCI_C BE2 PCI_S TOP PCI_C BE1 PCI_A D13 PCI_A D10 PCI_A D05
VDD_I O PCI_P ERR VSS PCI_A D14 PCI_A D11 VDD_I O
M
VSS EMB_ AD09 EMB_ AD14 VDD_I O EMB_ AD18
VSS EMB_ AD07 EMB_ AD13 VDD_I O EMB_ AD21
VSS
VSS
VSS
VSS
VSS
VSS
N
VDD_I O VDD_I O
VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE
VSS
VSS
VSS
VSS
VSS
VSS
VDD_I O VDD_I O
PCI_P AR PCI_C BE0 PCI_A D03 SYS_ PLL_A VDD SYS_ PLL_A VSS SRES ET
P
VSS
VSS
VSS
VSS
VSS
VSS
R
VSS
VSS
VSS
VSS
VSS
VSS
T
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U
EMB_ AD25 EMB_ AD26 EMB_ AD31 LPC_ CS2
VSS
EMB_ AD24 EMB_ AD28 EMB_ AX02 LPC_ CS1
VSS
EMB_ AD29 EMB_ AX01 LPC_ CS0 LPC_ OE
VSS
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VSS
PCI_I NTA
PCI_A D00 SYS_ XTALI HRES ET
PCI_A D02
PCI_A D04 PCI_A D01 SYS_ XTALO CKST P_OU T
V
EMB_ AD27 EMB_ AX00 VDD_I O
EMB_ AD30 LPC_A X03 VDD_I O
VSS PORE SET
VSS
W
VDD_I O
VDD_I O
TDO
TEST
Y
J1850 _TX VDD_ MEM_I O MVTT 0 MDQ1 0 VDD_ VDD_ MEM_I MEM_I O O MDQ1 9 MDQ2 1 MDQ2 7 MDQ3 1 CORE _PLL_ AVDD VDD_ MEM_I O
TDI
VSS
TMS
AA
LPC_ RWB
LPC_A PSC4_ CK 1
LPC_ CLK
PSC4_ 3
VSS
VSS
VSS
VSS
VSS
VSS
I2C2_ SDA
VDD_I O
J1850 _RX
VDD_I O
TRST
AB
PSC4_ 0
VSS
PSC4_ 2
VSS
PSC3_ MDQ1 1
MDQ5
VSS
MVRE F
MA1
MA5
MA14
MCKE
SPDIF _TXCL K
I2C1_ SCL
I2C1_ SDA
VSS
IRQ1
TCK
AC
VDD_ PSC5_ PSC4_ PSC5_ PSC3_ MEM_I MDM0 0 4 1 2 O PSC5_ PSC5_ 2 3 PSC3_ MDQS 3 0
MDQ8
VSS
VDD_ MDQ1 MDQS MEM_I 4 2 O MDQ1 8
VSS
VDD_ MDQ2 MDQ3 MEM_I 5 0 O MDQ2 3 MDQS 3 MDQ2 9
MBA1
VSS
MA7
MA11
VDD_ MEM_I MODT O
VSS
I2C0_ SCL CORE _PLL_ AVSS
SPDIF _RX
I2C2_ SCL
IRQ0
AD
VSS
MDQ6
MDQ1 1
VDD_ MDQS MDQ1 MEM_I 1 6 O VDD_ MDQ1 MEM_I 2 O MVTT 1 MDQ1 3
MDQ2 0
MBA0
MA0
MA4
MA9
MA13
MWE
MCS
SPDIF _TX
VSS
I2C0_ SDA
AE
VDD_I O
VDD_ VDD_I PSC5_ MDQ2 MEM_I MDQ7 O 4 O VDD_I PSC3_ PSC3_ MDQ0 O 0 4 MDQ3
VSS
MDM1
MVTT 2 MDQ1 5
VSS
MDQ2 4
MVTT 3 MDQ2 2
VDD_ MDQ2 MEM_I 8 O MDQ2 6 MDM3
VSS
MA2
MA6
VDD_ MEM_I O MA3
MA12
MA15
VSS
VDD_I O
VDD_I O VDD_I O
VSS
AF
MDQ4
MDQ9
MDQ1 7
MDM2
MCK
MCK
MBA2
MA8
MA10
MRAS
MCAS
Figure 63. Ball Map for the MPC5121E 516-PBGA Package
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
83
Package Information
Figure 64 shows the mechanical dimensions and bottom surface nomenclature of the MPC5121E/MPC5123 516-PBGA package.
Figure 64. Mechanical Dimension and Bottom Surface Nomenclature of the MPC5121E/MPC5123 TEPBGA
1 2
All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
MPC5121E/MPC5123 Data Sheet, Rev. 1 84
Preliminary
Freescale Semiconductor
Product Documentation
6
Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Table 54 provides a revision history for this document. Table 54. Document Revision History
Revision Rev. 0, DraftA Rev. 0, DraftB Rev. 0, DraftC First Draft (5/2008) Second Draft (5/2008) Third Draft (7/2008) Substantive Change(s)
MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor
Preliminary
85
THIS PAGE INTENTIONALLY BLANK
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Document Number: MPC5121E
Rev. 1 10/2008
Preliminary

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